MIMO Hardware Simulator Design for Outdoor Time-Varying Heterogeneous Channels

1-4International audienceThis paper presents a hardware simulator of Multiple- Input Multiple-Output (MIMO) propagation channels. The hardware simulator reproduces a desired radio channel and makes it possible to test "on table" different MIMO systems. A specific architecture of the digital block of the simulator is presented to characterize an outdoor scenario for Long Term Evolution (LTE) systems. An algorithm is introduced to switch between the impulse responses and to control the time variation of the delays. The new architecture is designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Its accuracy, occupation on the FPGA and latency are analyzed

Iterative transceiver design for MIMO AF relay networks with multiple sources

This paper addresses the problem of transceiver design for an amplify-and-forward relay network with multiple sources, multiple relays and multiple destinations. Each node in the network is assumed to be equipped with multiple antennas. A general iterative algorithm is proposed based on convex quadratic optimization theory to minimize mean-square-error of the recovered signals at the destinations. Its convergence and extensions to other scenarios are also discussed. Finally, the effectiveness of the proposed iterative algorithm is demonstrated by computer simulations. ©2010 IEEE.published_or_final_versionThe IEEE Military Communications Conference (MILCOM 2010), San Jose, CA., 31 October-3 November 2010. In Proceedings of MILCOM, 2010, p. 369-37

Bayesian robust linear transceiver design for dual-hop amplify-and-forward MIMO relay systems

In this paper, we address the robust linear transceiver design for dual-hop amplify-and-forward (AF) MIMO relay systems, where both transmitters and receivers have imperfect channel state information (CSI). With the statistics of channel estimation errors in the two hops being Gaussian, we formulate the robust linear-minimum-mean-square-error (LMMSE) transceiver design problem using the Bayesian framework, and derive a closed-form solution. Simulation results show that the proposed algorithm reduces the sensitivity of the relay system to channel estimation errors, and performs better than the algorithm using estimated channel only.published_or_final_versionThe IEEE Global Telecommunications Conference (GLOBECOM 2009), Honolulu, HI., 30 November-4 December 2009. In Proceedings of GLOBECOM, 2009, p. 1-

Hardware Simulator: Digital Block Design for Time- Varying MIMO Channels with TGn Model B Test

International audienceA hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. Thus, it makes possible to ensure the same test conditions in order to compare the performance of various equipments. This paper presents new frequency domain and time domain architectures of the digital block of a hardware simulator of MIMO propagation channels. The two architectures are tested with WLAN 802.11ac standard, in indoor environment, using time-varying TGn 802.11n channel model B. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed

Joint Source and Relay Optimization for Parallel MIMO Relay Networks

In this article, we study the optimal structure of the source precoding matrix and the relay amplifying matrices for multiple-input multiple-output (MIMO) relay communication systems with parallel relay nodes. Two types of receivers are considered at the destination node: (1) The linear minimal mean-squared error (MMSE) receiver; (2) The nonlinear decision feedback equalizer based on the minimal MSE criterion. We show that for both receiver schemes, the optimal source precoding matrix and the optimal relay amplifying matrices have a beamforming structure. Using such optimal structure, joint source and relay power loading algorithms are developed to minimize the MSE of the signal waveform estimation at the destination. Compared with existing algorithms for parallel MIMO relay networks, the proposed joint source and relay beamforming algorithms have significant improvement in the system bit-error-rate performance

Linear transceiver design for amplify-and-forward MIMO relay systems under channel uncertainties

Proceedings of the IEEE Wireless Communications and Networking Conference, 2010, p. 1-6In this paper, robust joint design of linear relay precoders and destination equalizers for amplify-and-forward (AF) MIMO relay systems under Gaussian channel uncertainties is investigated. After incorporating the channel uncertainties into the robust design based on the Bayesian framework, a closed-form solution is derived to minimize the mean-square-error (MSE) of the received signal at the destination. The effectiveness of the proposed robust transceiver is verified by simulations. ©2010 IEEE.published_or_final_versionThe IEEE Wireless Communications and Networking Conference (WCNC), Sydney, Australia, 18-21 April 2010. In Proceedings of WCNC, 2010, p. 1-

Linear Precoding for Relay Networks with Finite-Alphabet Constraints

In this paper, we investigate the optimal precoding scheme for relay networks with finite-alphabet constraints. We show that the previous work utilizing various design criteria to maximize either the diversity order or the transmission rate with the Gaussian-input assumption may lead to significant loss for a practical system with finite constellation set constraint. A linear precoding scheme is proposed to maximize the mutual information for relay networks. We exploit the structure of the optimal precoding matrix and develop a unified two-step iterative algorithm utilizing the theory of convex optimization and optimization on the complex Stiefel manifold. Numerical examples show that this novel iterative algorithm achieves significant gains compared to its conventional counterpart.Comment: Accepted by IEEE Int. Conf. Commun. (ICC), Kyoto, Japan, 201

Hardware simulator design for LTE applications with time-varying MIMO channels

International audienceA hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents new frequency domain and time domain architectures of the digital block of a hardware simulator of MIMO propagation channels. The two architectures are tested with LTE standard, in outdoor environment, using time-varying channels. The new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed. The result shows that the architectures produce low occupation on the FPGA and have a small relative error of the output signals