СВЕРТКА РЕГУЛЯРНЫХ МАТРИЧНЫХ СТРУКТУР ЗАКАЗНЫХ СБИС МЕТОДОМ МОДЕЛИРОВАНИЯ ОТЖИГА

Рассматривается задача топологической оптимизации программируемых логических матрицметодом свертки. Предлагаются алгоритмы многократной и простой сверток регулярных струк-тур СБИС на основе моделирования отжига, позволяющие находить оптимальное или близкое к нему решение задачи свертки. Приводятся результаты исследования предложенных алгоритмов свертки

Reconfigurable hardware for control applications

This portfolio document is intended to present the work carried out in order to meet the requirements of the Engineering Doctorate (EngD) program undertaken at the Institute for System Level Integration (ISLI). This program was undertaken in partnership with the Universities of Glasgow, Edinburgh, Strathclyde and Heriott Watt and was funded by EPSRC and SLI Ltd. The use of control systems is becoming ubiquitous with even the simplest of systems now employing some kind of control logic. For this reason the project investigated the use and development of reconfigurable hardware for control applications. This first involved a detailed analysis of the current state of the art in the reconfigurable field as well as some selected applications where it is thought this technology may be of benefit. The main body of the project was separated into three distinct areas of research and is hence presented as a collection of three technical documents. The first of these areas was the use of reconfigurable hardware for the implementation of Finite State Machines (FSM) with particular reference to reducing the size of the hardware block required to implement these structures. From this a novel implementation method was developed based on the principle of Forward Transition Expressions which are capable of implementing FSMs on a reconfigurable device using run-time reconfiguration. The second area of research was the investigation of the characteristics of reconfigurable devices with a view to estimating the amount of hardware required within a device from high level parameters. The final area of research was the development of a custom reconfigurable device specifically tailored for the implementation of FSM

Optimization of programmable logic arrays

We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determined that is especially suited for row segmentation. An upper bound and a lower bound for the number of rows in the segmented PLA are derived. Furthermore, it is shown how the result can be improved upon by the duplication of some of the inputs