9,857 research outputs found

    Wildcard dimensions, coding theory and fault-tolerant meshes and hypercubes

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    Hypercubes, meshes and tori are well known interconnection networks for parallel computers. The sets of edges in those graphs can be partitioned to dimensions. It is well known that the hypercube can be extended by adding a wildcard dimension resulting in a folded hypercube that has better fault-tolerant and communication capabilities. First we prove that the folded hypercube is optimal in the sense that only a single wildcard dimension can be added to the hypercube. We then investigate the idea of adding wildcard dimensions to d-dimensional meshes and tori. Using techniques from error correcting codes we construct d-dimensional meshes and tori with wildcard dimensions. Finally, we show how these constructions can be used to tolerate edge and node faults in mesh and torus networks

    A Study on the Noise Threshold of Fault-tolerant Quantum Error Correction

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    Quantum circuits implementing fault-tolerant quantum error correction (QEC) for the three qubit bit-flip code and five-qubit code are studied. To describe the effect of noise, we apply a model based on a generalized effective Hamiltonian where the system-environment interactions are taken into account by including stochastic fluctuating terms in the system Hamiltonian. This noise model enables us to investigate the effect of noise in quantum circuits under realistic device conditions and avoid strong assumptions such as maximal parallelism and weak storage errors. Noise thresholds of the QEC codes are calculated. In addition, the effects of imprecision in projective measurements, collective bath, fault-tolerant repetition protocols, and level of parallelism in circuit constructions on the threshold values are also studied with emphasis on determining the optimal design for the fault-tolerant QEC circuit. These results provide insights into the fault-tolerant QEC process as well as useful information for designing the optimal fault-tolerant QEC circuit for particular physical implementation of quantum computer.Comment: 9 pages, 9 figures; to be submitted to Phys. Rev.

    Implementation of Fault-tolerant Quantum Logic Gates via Optimal Control

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    The implementation of fault-tolerant quantum gates on encoded logic qubits is considered. It is shown that transversal implementation of logic gates based on simple geometric control ideas is problematic for realistic physical systems suffering from imperfections such as qubit inhomogeneity or uncontrollable interactions between qubits. However, this problem can be overcome by formulating the task as an optimal control problem and designing efficient algorithms to solve it. In particular, we can find solutions that implement all of the elementary logic gates in a fixed amount of time with limited control resources for the five-qubit stabilizer code. Most importantly, logic gates that are extremely difficult to implement using conventional techniques even for ideal systems, such as the T-gate for the five-qubit stabilizer code, do not appear to pose a problem for optimal control.Comment: 18 pages, ioptex, many figure

    Overhead and noise threshold of fault-tolerant quantum error correction

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    Fault tolerant quantum error correction (QEC) networks are studied by a combination of numerical and approximate analytical treatments. The probability of failure of the recovery operation is calculated for a variety of CSS codes, including large block codes and concatenated codes. Recent insights into the syndrome extraction process, which render the whole process more efficient and more noise-tolerant, are incorporated. The average number of recoveries which can be completed without failure is thus estimated as a function of various parameters. The main parameters are the gate (gamma) and memory (epsilon) failure rates, the physical scale-up of the computer size, and the time t_m required for measurements and classical processing. The achievable computation size is given as a surface in parameter space. This indicates the noise threshold as well as other information. It is found that concatenated codes based on the [[23,1,7]] Golay code give higher thresholds than those based on the [[7,1,3]] Hamming code under most conditions. The threshold gate noise gamma_0 is a function of epsilon/gamma and t_m; example values are {epsilon/gamma, t_m, gamma_0} = {1, 1, 0.001}, {0.01, 1, 0.003}, {1, 100, 0.0001}, {0.01, 100, 0.002}, assuming zero cost for information transport. This represents an order of magnitude increase in tolerated memory noise, compared with previous calculations, which is made possible by recent insights into the fault-tolerant QEC process.Comment: 21 pages, 12 figures, minor mistakes corrected and layout improved, ref added; v4: clarification of assumption re logic gate

    Fault-tolerant multichannel demultiplexer subsystems

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    Fault tolerance in future processing and switching communication satellites is addressed by showing new methods for detecting hardware failures in the first major subsystem, the multichannel demultiplexer. An efficient method for demultiplexing frequency slotted channels uses multirate filter banks which contain fast Fourier transform processing. All numerical processing is performed at a lower rate commensurate with the small bandwidth of each bandbase channel. The integrity of the demultiplexing operations is protected by using real number convolutional codes to compute comparable parity values which detect errors at the data sample level. High rate, systematic convolutional codes produce parity values at a much reduced rate, and protection is achieved by generating parity values in two ways and comparing them. Parity values corresponding to each output channel are generated in parallel by a subsystem, operating even slower and in parallel with the demultiplexer that is virtually identical to the original structure. These parity calculations may be time shared with the same processing resources because they are so similar
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