2 research outputs found
Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies
Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep
nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on
a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge
is to reliably and efficiently take the full advantage of the unprecedented computing power
offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the
limitations of both the interconnecting wires and semiconductor devices in integrated circuits
have to be addressed.
At the interconnect level, the major challenge in current high density integrated circuit
is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these
problems require better analysis of interconnect resistance, inductance, and capacitance.
Therefore, this dissertation has proposed a new delay model and analyzed the time-domain
output response of complex poles, real poles, and double poles for resistance-inductance
capacitance interconnect network based on a second order approximate transfer function. Both
analytical models and simulation results show that the real poles model is much faster than the
complex poles model, and achieves significantly higher accuracy in order to characterize the
overshoot and undershoot of the output responses.
On the other hand, the semiconductor industry is anticipating that within a decade
silicon devices will be unable to meet the demands at nanoscale due to dimension and material
scaling. Recently, molybdenum disulfide (MoSâ‚‚) has emerged as a new super material to
replace silicon in future semiconductor devices. Besides, conventional field effect transistor
technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit
requires adoption of new devices based on tunneling mechanism. Keeping the above
mentioned trends, this dissertation also proposed a multilayer MoSâ‚‚ channel-based tunneling
transistor and identifies the fundamental parameters and design specifications that need to be
optimized in order to achieve higher ON-currents. A simple analytical model of the proposed
device is derived by solving the time-independent Schrodinger equation. It is analytically
proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing
(S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode