A 100-MIPS GaAs asynchronous microprocessor

The authors describe how they ported an asynchronous microprocessor previously implemented in CMOS to gallium arsenide, using a technology-independent asynchronous design technique. They introduce new circuits including a sense-amplifier, a completion detection circuit, and a general circuit structure for operators specified by production rules. The authors used and tested these circuits in a variety of designs

Design and manufacturing of a Selective Laser Sintering test bench to test sintering materials

The goal of this project is to design and build a prototype of recoating system for a laser cutting machine to turn it into a selective laser sintering printing machine. This prototype will be used to study new sintering materials and to design, if decided, a SLS 3D printing Machine (Selective Laser Sintering). This project has been developed in the installations and funded by Fundació CIM. The project develops the mechanical design and the electronic system design. Both parts are explained on this paper, so new users can use the machine and can understand the system. With this paper, it is expected that it can be improved in a future to test other parameters and configurations. The paper is divided in three basic blocks that are summed up here: The first block is an introduction to the 3D printing technologies. The most used of them are explained and selective laser sintering is explained in deep. With this block the reader can understand why it is important to develop the SLS technology and what has to be done to improve the machines and the technology. The second block is a discussion on the mechanical design of the machine. The general idea of the machine is explained so the user can understand why the machine is designed in this way. After that, each part is detailed to see how the different mechanical challenges where overtaken. At the end of the block, there is a small calculations section needed on the electronic part. The third block is an extensive explanation of the electronic system that controls and moves the machine. In that block, the different components are explained so the user can understand its basics working principles. It is also explained how the selection of the electronic components was done. Then everything is put together to see the whole electronic system. Along with this paper, there are annexes that provide some extra information for the reader. One of this annexes refers to the mechanical part and the other one has some datasheets and coding for the electronic section. The whole design has been done in SOLIDWORKS cad software and its electric extension ELECWORKS. The programming job was done with Arduino compiler

High-speed, in-band performance measurement instrumentation for next generation IP networks

Facilitating always-on instrumentation of Internet traffic for the purposes of performance measurement is crucial in order to enable accountability of resource usage and automated network control, management and optimisation. This has proven infeasible to date due to the lack of native measurement mechanisms that can form an integral part of the network‟s main forwarding operation. However, Internet Protocol version 6 (IPv6) specification enables the efficient encoding and processing of optional per-packet information as a native part of the network layer, and this constitutes a strong reason for IPv6 to be adopted as the ubiquitous next generation Internet transport. In this paper we present a very high-speed hardware implementation of in-line measurement, a truly native traffic instrumentation mechanism for the next generation Internet, which facilitates performance measurement of the actual data-carrying traffic at small timescales between two points in the network. This system is designed to operate as part of the routers' fast path and to incur an absolutely minimal impact on the network operation even while instrumenting traffic between the edges of very high capacity links. Our results show that the implementation can be easily accommodated by current FPGA technology, and real Internet traffic traces verify that the overhead incurred by instrumenting every packet over a 10 Gb/s operational backbone link carrying a typical workload is indeed negligible

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER