184,943 research outputs found
Optical interconnection networks based on microring resonators
Optical microring resonators can be integrated on a chip to perform switching operations directly in the optical domain. Thus they become a building block to create switching elements in on-chip optical interconnection networks, which promise to overcome some of the limitations of current electronic networks. However, the peculiar asymmetric power losses of microring resonators impose new constraints on the design and control of on-chip optical networks. In this work, we study the design of multistage interconnection networks optimized for a particular metric that we name the degradation index, which characterizes the asymmetric behavior of microrings. We also propose a routing control algorithm to maximize the overall throughput, considering the maximum allowed degradation index as a constrain
Leakage-Aware Interconnect for On-Chip Network
On-chip networks have been proposed as the interconnect fabric for future
systems-on-chip and multi-processors on chip. Power is one of the main
constraints of these systems and interconnect consumes a significant portion of
the power budget. In this paper, we propose four leakage-aware interconnect
schemes. Our schemes achieve 10.13%~63.57% active leakage savings and
12.35%~95.96% standby leakage savings across schemes while the delay penalty
ranges from 0% to 4.69%.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
Local Quantum Dot Tuning on Photonic Crystal Chips
Quantum networks based on InGaAs quantum dots embedded in photonic crystal
devices rely on QDs being in resonance with each other and with the cavities
they are embedded in. We developed a new technique based on temperature tuning
to spectrally align different quantum dots located on the same chip. The
technique allows for up to 1.8nm reversible on-chip quantum dot tuning
Channel Characterization for Chip-scale Wireless Communications within Computing Packages
Wireless Network-on-Chip (WNoC) appears as a promising alternative to
conventional interconnect fabrics for chip-scale communications. WNoC takes
advantage of an overlaid network composed by a set of millimeter-wave antennas
to reduce latency and increase throughput in the communication between cores.
Similarly, wireless inter-chip communication has been also proposed to improve
the information transfer between processors, memory, and accelerators in
multi-chip settings. However, the wireless channel remains largely unknown in
both scenarios, especially in the presence of realistic chip packages. This
work addresses the issue by accurately modeling flip-chip packages and
investigating the propagation both its interior and its surroundings. Through
parametric studies, package configurations that minimize path loss are obtained
and the trade-offs observed when applying such optimizations are discussed.
Single-chip and multi-chip architectures are compared in terms of the path loss
exponent, confirming that the amount of bulk silicon found in the pathway
between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on
Networks-on-Chip (NOCS 2018); Torino, Italy; October 201
Design and implementation of the Quarc network on-chip
Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip. However, to successfully replace its predecessor, the NoC has to be able to efficiently exchange all types of traffic including collective communications. The latter is especially important for e.g. cache updates in multicore systems. The Quarc NoC architecture has been introduced as a Networks-on-Chip which is highly efficient in exchanging all types of traffic including broadcast and multicast. In this paper we present the hardware implementation of the switch architecture and the network adapter (transceiver) of the Quarc NoC. Moreover, the paper presents an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs implemented in Verilog targeting the Xilinx Virtex FPGA family. We demonstrate a dramatic improvement in performance over the Spidergon especially for broadcast traffic, at no additional hardware cost
Scalability of broadcast performance in wireless network-on-chip
Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of cores. The main reason is that the performance of such networks drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.Peer ReviewedPostprint (published version
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