SIGNAL PROCESSING TECHNIQUES AND APPLICATIONS

As the technologies scaling down, more transistors can be fabricated into the same area, which enables the integration of many components into the same substrate, referred to as system-on-chip (SoC). The components on SoC are connected by on-chip global interconnects. It has been shown in the recent International Technology Roadmap of Semiconductors (ITRS) that when scaling down, gate delay decreases, but global interconnect delay increases due to crosstalk. The interconnect delay has become a bottleneck of the overall system performance. Many techniques have been proposed to address crosstalk, such as shielding, buffer insertion, and crosstalk avoidance codes (CACs). The CAC is a promising technique due to its good crosstalk reduction, less power consumption and lower area. In this dissertation, I will present analytical delay models for on-chip interconnects with improved accuracy. This enables us to have a more accurate control of delays for transition patterns and lead to a more efficient CAC, whose worst-case delay is 30-40% smaller than the best of previously proposed CACs. As the clock frequency approaches multi-gigahertz, the parasitic inductance of on-chip interconnects has become significant and its detrimental effects, including increased delay, voltage overshoots and undershoots, and increased crosstalk noise, cannot be ignored. We introduce new CACs to address both capacitive and inductive couplings simultaneously.Quantum computers are more powerful in solving some NP problems than the classical computers. However, quantum computers suffer greatly from unwanted interactions with environment. Quantum error correction codes (QECCs) are needed to protect quantum information against noise and decoherence. Given their good error-correcting performance, it is desirable to adapt existing iterative decoding algorithms of LDPC codes to obtain LDPC-based QECCs. Several QECCs based on nonbinary LDPC codes have been proposed with a much better error-correcting performance than existing quantum codes over a qubit channel. In this dissertation, I will present stabilizer codes based on nonbinary QC-LDPC codes for qubit channels. The results will confirm the observation that QECCs based on nonbinary LDPC codes appear to achieve better performance than QECCs based on binary LDPC codes.As the technologies scaling down further to nanoscale, CMOS devices suffer greatly from the quantum mechanical effects. Some emerging nano devices, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron transistors (SETs), have no such issues and are promising candidates to replace the traditional CMOS devices. Threshold gate, which can implement complex Boolean functions within a single gate, can be easily realized with these devices. Several applications dealing with real-valued signals have already been realized using nanotechnology based threshold gates. Unfortunately, the applications using finite fields, such as error correcting coding and cryptography, have not been realized using nanotechnology. The main obstacle is that they require a great number of exclusive-ORs (XORs), which cannot be realized in a single threshold gate. Besides, the fan-in of a threshold gate in RTD nanotechnology needs to be bounded for both reliability and performance purpose. In this dissertation, I will present a majority-class threshold architecture of XORs with bounded fan-in, and compare it with a Boolean-class architecture. I will show an application of the proposed XORs for the finite field multiplications. The analysis results will show that the majority class outperforms the Boolean class architectures in terms of hardware complexity and latency. I will also introduce a sort-and-search algorithm, which can be used for implementations of any symmetric functions. Since XOR is a special symmetric function, it can be implemented via the sort-and-search algorithm. To leverage the power of multi-input threshold functions, I generalize the previously proposed sort-and-search algorithm from a fan-in of two to arbitrary fan-ins, and propose an architecture of multi-input XORs with bounded fan-ins

Caractérisation et modélisation d'interconnexions. Développement de nouvelles solutions pour la transmission d'informations au sein des cartes et puces électroniques.

Since the first IC in 1959 the performances and computing capacity of electronic devices have always grown, following thus the well-known empirical Moore’s law which says that the number of transistors in a dense integrated circuit doubles approximately every 18 months. This prevision is still verified even if some limitations appears like for example the limitation of the clock frequency which grow less than the projection that the ITRS (International Technology Roadmap for Semiconductors) has made in 2000. One of the stumbling point comes from interconnects which ensure the transmission of information inside electronic chips or cards. The interconnects imply delay, signal distortion, crosstalk and power dissipation and they now must be taken into account during electronic device design. So the researches depicted in this manuscript deal with the modelling of interconnect and study of new solutions to overcome problems due to classical interconnects. These works have been realized in Lab-STICC laboratory with the help of colleagues, post-doc, PhDs and Master Students. The manuscript include three chapters, the first one concerns researches on modelling aspects, the second is about alternative solutions to classical wired interconnects and to conclude the research projects for the next years are presented.The first chapter concern researches about modelling which aim to develop reliable models in view to simulate more quickly the electrical behavior of interconnects. Firstly the collaborations concerning the development of model-order reduction are presented. Then with the aim to evaluate the impact of inductive behavior, the current return patch problem and so the extraction of loop inductance is treated. The 3D discontinuities and 3D environment effects are presented in the third part of this chapter. For example the parallel grid influences on propagation are explored as well as the case of coupling between microvias and parallel-plates cavities inside multilayer PCB.The second chapter is about research of new solutions to overcome the limitation due to classical wired interconnects. A review of envisaged alternative solutions like for example optical interconnects and CNT (carbon Nano Tube) is first presented. Then a focus on RF guided interconnect is made and constraints in term of bandwidth are explained and some coupling techniques are explored. These studies naturally lead to exploration of the paradigm of wireless interconnects and the preliminary researches on radio transmission between two circuits placed on a PCB are shown. All these approaches of RF wireless interconnect are prelude to the research projects which are developed in a third chapter of the manuscript.The development of the draft over 4 years is based on the BBC project (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) funded by the Labex COMINLABS and which will begin in October 2016. The aims of this project are outlined as well as the aims of another project entitled “BROADWAYS” (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) which is currently in the second step of review by the ANR. To conclude this research part other embryonic researches are presented as well as long term researches envisaged like terahertz applications of the use of graphene for microwave applications.Depuis les premiers circuits intégrés en 1959 les composants et les systèmes électroniques n’ont cessé de voir leurs performances augmenter suivant ainsi la loi empirique de Gordon Moore qui prévoit un doublement de la complexité des circuits tous les 18 mois. Cette prévision reste aujourd’hui toujours vérifiée même si nous constatons depuis une dizaine d’années que les fréquences d’horloges stagnent autour de 4-5 GHz alors que l’ITRS (International Technology Roadmap for Semiconductors) prévoyait dans les années 2000 des fréquences de travail pouvant atteindre 40 GHz pour 2016. L’un des facteurs limitant la progression des performances vient des interconnexions métalliques servant au transport de l’information au sein des systèmes électroniques. Les travaux de recherche présentés dans le cadre de l’obtention de l‘habilitation à diriger des recherches concernent d’une part les travaux réalisés sur la modélisation des interconnexions et d’autre part ceux sur l’étude de solutions alternatives à ces interconnexions classiques. Ces travaux ont été réalisés au sein du Lab-STICC en collaboration avec plusieurs collègues et lors de l’encadrement de plusieurs post-doctorants, doctorants et stagiaires de master recherche. Le mémoire comporte trois chapitres principaux, le premier concerne les travaux sur la modélisation des interconnexions, le second porte sur l’étude de solutions alternatives à ces interconnexions classiques et le dernier permet la présentation des projets de recherches pour les prochaines années.L’objectif de nos travaux sur la modélisation des interconnexions consiste au développement de modèles fiables permettant d’appréhender leurs effets sur les signaux. Dans un premier temps, les travaux portant sur l’obtention de modèles à complexité réduite sont présentés. Puis, afin d’évaluer l’impact des effets inductifs des interconnexions, nous présentons les travaux sur l’identification des chemins de retours du courant dans un réseau comprenant plusieurs lignes et qui sont nécessaires pour déterminer les inductances de boucles. La prise en compte de l’environnement 3D des interconnexions fait l’objet de la troisième partie de ce chapitre. Nous traitons ainsi de l’influence de différentes discontinuités et nous présentons des règles de design permettant la limitation des risques de conversion de mode de propagation. Dans le cadre de structures multicouches, nous abordons l’influence de grilles métalliques placées au voisinage d’une ligne sur la propagation des signaux. Enfin nous traitons des risques de couplage entre des vias et les modes de cavités au sein des structures PCB multicouches.La seconde thématique développée dans ce mémoire porte sur le développement de solutions alternatives aux interconnexions classiques. Après avoir listé certaines de ces solutions telle que les interconnexions optiques ou les nanotubes de carbone, nous présentons plus particulièrement les interconnexions RF qui véhiculent l’information numérique sur porteuse à haute fréquence. Dans un premier temps nous analysons les interconnexions RF guidées qui utilisent une ligne de transmission comme support pour transporter l’information. A partir de l’étude des modes d’accès multiples nous montrons que les canaux doivent être large bande et nous explorons diverses façons de transmettre l’énergie à la ligne de transmission. Enfin nous présentons quelques exemples de performances obtenues à l’aide de démonstrateurs numériques. Ces études des interconnexions RF guidées nous ont naturellement amené à considérer les possibilités de transmission par voie hertzienne des informations au sein des cartes et puces électroniques. Nous avons ainsi analysé à l’aide de démonstrateurs très simples les niveaux de transmission entre deux circuits placés sur une même carte PCB (Printed Circuit Board).Ces études initiales sur les interconnexions radios ou sans fils servent de point d’appui aux projets de recherche présentés à la fin de ce manuscrit. La philosophie du projet BBC (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) financé par le Labex COMINLABS à partir d’octobre est présenté de même que celle du projet ANR Broadways (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) en seconde phase d’étude auprès de l’ANR