Fully digital-compatible built-in self-test solutions to linearity testing of embedded mixed-signal functions

Mixed-signal circuits, especially analog-to-digital and digital-to-analog converters, are the most widely used circuitry in electronic systems. In the most of the cases, mixed-signal circuits form the interface between the analog and digital worlds and enable the processing and recovering of the real-world information. Performance of mixed-signal circuits, such as linearity and noise, are then critical to any applications. Conventionally, mixed-signal circuits are tested by mixed-signal automatic test equipment (ATE). However, along with the continuous performance improvement, using conventionally methods increases test costs significantly since it takes much more time to test high-performance parts than low-performance ones and mixed-signal ATE testers could be extremely expensive depending on the test precision they provide. Another factor that makes mixed-signal testing more and more challenging is the advance of the integration level. In the popular system-on-chip applications, mixed-signal circuits are deeply embedded in the systems. With less observability and accessibility, conventionally external test methods can not guarantee the precision of the source signals and evaluations. Test performance is then degraded. This work investigates new methods using digital testers incorporated with on-chip, built-in self-test circuits to test the linearity performance of data converters with less test cost and better test performance. Digital testers are cheap to use since they only offer logic signals with direct connections. The analog sourcing and evaluation capabilities have to be absorbed by the on-chip BIST circuits, which, meanwhile, could benefit the test performance with access to the internal circuit nodes. The main challenge of the digital-compatible BIST methods is to implement the BIST circuits with enough high test performance but with low design complexity and cost. High-resolution data converter testing needs much higher-precision analog source signals and evaluation circuits. However, high-precision analog circuits are conventionally hard to design and costly, and their performance is subject to mismatch errors and process variations and cannot be guaranteed without careful testing. On the digital side, BIST circuits usually conduct procedure control and data processing. To make the BIST solution more universal, the control and processing performed by the digital BIST circuits should be simple and not rely on any complex microcontroller and DSP block. Therefore, the major tasks of this dissertation are 1) performance-robust analog BIST circuit design and 2) test procedure development. Analog BIST circuits in this work consist of only low-accuracy analog components, which are usually easy to design and cost effective. The precision is then obtained by applying the so-called deterministic dynamic element matching technique to the low-accuracy analog cells. The test procedure and data processing designed for the BIST system are simple and can be implemented by small logic circuits. In this dissertation, we discuss the proposed BIST solutions to ADC and DAC linearity testing in chapter 3 and chapter 5, respectively. In each case, the structure of the test system, the test procedure, and the theoretical analysis of the test performance are presented. Simulation results are shown to verify the efficacy of the methods. The ADC BIST system is also verified experimentally. In addition, chapter 4 introduces a system-identification based reduced-code testing method for pipeline ADCs. This method is able to reduce test time by more than 95%. And it is compatible with the proposed BIST method discussed in chapter 3

Deterministic dynamic element matching: an enabling technology for SoC built-in-self-test

The analog-to-digital converter (ADC) is a key building block of today\u27s high-volume systems-on-a-chip (SoCs). Built-in-self-test (BIST) is the most promising solution to testing deeply-embedded ADCs. Cost-effective stimulus source with on-chip integrability has been viewed as the bottleneck of ADC BIST, and consequentially the bottleneck of SoC BIST and BIST-based self-calibration. The deterministic dynamic element matching (DDEM) technique has been proposed as a solution to this problem;In this work, rigorous theoretical analysis is presented to show the performance of a DDEM digital-to-analog converter (DAC) as an ADC linearity test stimulus source. Guided by the insight obtained this analysis, a systematic approach for cost-effective DDEM DAC design is proposed. Two generations of DDEM DACs have been designed, fabricated, and measured. 12-bit equivalent linearity was achieved from the first DDEM DAC with 8-bit apparent resolution and less than 5-bit raw linearity after systematic error compensation. The achieved 12-bit linearity outperforms any on-chip stimulus source in literature. Based on the first design, a new DDEM DAC with 12-bit apparent resolution, 10-bit raw linearity, and 9-bit DDEM switching was designed with improved design technique. This DAC was fabricated in standard 0.5-pm CMOS technology with a core die area of 2 mm2. Clear ramp signals could be observed on an oscilloscope when the DDEM DAC was clocked at 100 MHz. Laboratory testing results confirmed that the new DDEM DAC achieved at least a 16-bit equivalent linearity; this was limited by the available instrumentation, which has 18-bit linearity. It outperforms any previously reported on-chip stimulus source in terms of ADC BIST performance by 5 bits. The robust performance, low cost, and short design cycle for on-chip implementation make DDEM an enabling technology for SoC BIST and self-calibration;Two new approaches based on DDEM are developed to further boost the die area efficiency, improving the basic DDEM approach. The first is termed segmented DDEM, and the second is dither-incorporated DDEM (DiDDEM). It has been shown through mathematical analysis and simulation that these can maintain the performance of the basic DDEM approach while greatly reducing the implementation cost

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

On-Chip At-Speed Linearity Testing of High-resolution High-Speed DACs Using DDEM ADCs with Dithering

Abstract-On-chip testing of high-resolution high-speed DACs is extremely challenging because of the stringent requirements on the accuracy, speed and cost of the measurement circuits. This work proposed a new on-chip strategy for DAC linearity testing applying the proposed deterministic dynamic element matching (DDEM) technique. Low-accuracy two-step flash ADCs are used as test devices. Speed advantage of flash structure enables at-speed testing, while its accuracy and resolution are improved by DDEM algorithm, the second stage and dithering. In this paper, the architecture of the DDEM flash ADC and DDEM algorithm are described. The design consideration of the major circuit blocks are talked about. The test performance is analyzed theoretically and verified by simulation. Simulation shows that a dithering incorporated two-step flash DDEM ADC, which consists of a 6-bit coarse DDEM stage, a 6-bit fine stage and a 5-bit dithering DAC, with linearity of all the blocks only at about 6-bit level, is capable of testing 14-bit DACs