Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems

We present a method for the automatic generation of netlists describing general three-dimensional electrothermal and electromagnetic field problems. Using a pair of structured orthogonal grids as spatial discretisation, a one-to-one correspondence between grid objects and circuit elements is obtained by employing the finite integration technique. The resulting circuit can then be solved with any standard available circuit simulator, alleviating the need for the implementation of a custom time integrator. Additionally, the approach straightforwardly allows for field-circuit coupling simulations by appropriately stamping the circuit description of lumped devices. As the computational domain in wave propagation problems must be finite, stamps representing absorbing boundary conditions are developed as well. Representative numerical examples are used to validate the approach. The results obtained by circuit simulation on the generated netlists are compared with appropriate reference solutions.Comment: This is a pre-print of an article published in the Journal of Computational Electronics. The final authenticated version is available online at: https://dx.doi.org/10.1007/s10825-019-01368-6. All numerical results can be reproduced by the Matlab code openly available at https://github.com/tc88/ANTHE

A Manufacturer Design Kit for Multi-Chip Power Module Layout Synthesis

The development of Multi-Chip Power Modules (MCPMs) has been a key factor in recent advancements in power electronics technologies. MCPMs achieve higher power density by combining multiple power semiconductor devices into one package. The work detailed in this thesis is part of an ongoing project to develop a computer-aided design software tool known as PowerSynth for MCPM layout synthesis and optimization. This thesis focuses on the definition and design of a Manufacturer Design Kit (MDK) for PowerSynth, which enables the designer to design an MCPM for a manufacturer’s fabrication process. The MDK is comprised of a layer stack and technology library, design rule checking (DRC), and layout versus schematic checking. File formats have been defined for layer stack and design rule input, and import functions have been written and integrated with the existing user interface and data structures to allow PowerSynth to accept these file formats as a form of input. Finally, an exhaustive DRC function has been implemented to allow the designer to verify that a synthesized layout meets all design rules before committing the design to manufacturing. This function was validated by running DRC on an example layout solution using two different sets of design rules

Effective electrothermal analysis of electronic devices and systems with parameterized macromodeling

We propose a parameterized macromodeling methodology to effectively and accurately carry out dynamic electrothermal (ET) simulations of electronic components and systems, while taking into account the influence of key design parameters on the system behavior. In order to improve the accuracy and to reduce the number of computationally expensive thermal simulations needed for the macromodel generation, a decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed. The approach is applied to study the impact of layout variations on the dynamic ET behavior of a state-of-the-art 8-finger AlGaN/GaN high-electron mobility transistor grown on a SiC substrate. The simulation results confirm the high accuracy and computational gain obtained using parameterized macromodels instead of a standard method based on iterative complete numerical analysis