5 research outputs found
Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations
Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources resulting in the migration of their application domain from prototype designing to low and medium volume production designing. Unfortunately most of the work pertaining to FPGA implementations does not focus on the technology dependent optimizations that can implement a desired functionality with reduced cost. In this paper we consider the mapping of simple ripple carry fixed-point adders (RCA) on look-up table (LUT) based FPGAs. The objective is to transform the given RCA Boolean network into an optimized circuit netlist that can implement the desired functionality with minimum cost. We particularly focus on 6-input LUTs that are inherent in all the modern day FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently and the result is compared against various adder designs. The implementation targets the XC5VLX30-3FF324 device from Xilinx Virtex-5 FPGA family. The cost of the circuit is expressed in terms of the resources utilized, critical path delay and the amount of on-chip power dissipated. Our implementation results show a reduction in resources usage by at least 50%; increase in speed by at least 10% and reduction in dynamic power dissipation by at least 30%. All this is achieved without any technology independent (architectural) modification
On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs
In this paper the use of Signed Digit (SD) Arithmetic to better exploit some of the architectural characteristic of the last generation FPGAs is presented. The implementation of Radix-4 SD adders, multipliers and Finite Impulse Response (FIR) filters has been carried out to demonstrate that the use of this number system representation optimally fits the 6-input LUT Logic Elements (LEs) of the newest FPGAs architectures. Comparisons of implementations of the same circuits by using 4-input LUT and 6-input LUT based FPGAs have been carried out showing that Radix-4 SD arithmetic is very efficiently implemented in the last generation FPGAS. © 2008 IEEE
Uso eficiente de aritmética redundante en FPGAs
Hasta hace pocos años, la utilización de aritmética redundante en FPGAs había
sido descartada por dos razones principalmente. En primer lugar, por el buen
rendimiento que ofrecían los sumadores de acarreo propagado, gracias a la lógica de
de acarreo que poseían de fábrica y al pequeño tamaño de los operandos en las
aplicaciones típicas para FPGAs. En segundo lugar, el excesivo consumo de área que
las herramientas de síntesis obtenían cuando mapeaban unidades que trabajan en carrysave.
En este trabajo, se muestra que es posible la utilización de aritmética redundante
carry-save en FPGAs de manera eficiente, consiguiendo un aumento en la velocidad de
operación con un consumo de recursos razonable. Se ha introducido un nuevo formato
redundante doble carry-save y se ha demostrado que la manera óptima para la
realización de multiplicadores de elevado ancho de palabra es la combinación de
multiplicadores empotrados con sumadores carry-save.Till a few years ago, redundant arithmetic had been discarded to be use in FPGA
mainly for two reasons. First, the efficient results obtained using carry-propagate adders
thanks to the carry-logic embedded in FPGAs and the small sizes of operands in typical
FPGA applications. Second, the high number of resources that the synthesis tools
utilizes to implement carry-save circuits.
In this work, it is demonstrated that carry-save arithmetic can be efficiently used
in FPGA, obtaining an important speed improvement with a reasonable area cost. A
new redundant format, double carry-save, has been introduced, and the optimal
implementation of large size multipliers has been shown based on embedded multipliers
and carry-save adders