High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio

High efficiency wideband low-power delta-sigma modulators

Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio

Novel structures for high-speed delta-sigma data converters

As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks. In this dissertation, low-power and wideband techniques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve power-efficient operation. Various double-sampling schemes are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell architecture is studied to insure higher performance when the number of modulators increases. 0.18 um double-poly/4-metal CMOS process was used to implement a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2*BW*2[superscript ENOB]) was 0.35 pJ/conversion, with a 16 mW power consumption. Measurement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR. A second-order noise-coupled modulator with an embedded-zero optimization was proposed to reduce power consumption by eliminating some of the integrators. This architecture makes easier the implementation of the small feedback capacitors for high OSR modulators

Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop delays (SLD) technique can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the active adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC. The second project describes two techniques to enhance the noise shaping function in the proposed low-distortion ΔΣ modulator with shifted loop delays. One is self-noise coupling based on low-distortion ΔΣ structure; the other is noise-coupled time-interleaved ΔΣ modulator. Both architectures use shifted loop delays to relax the critical timing constraints in the modulator feedback path, then to save power consumption of each block in the modulators. Two ΔΣ ADCs were analyzed and simulated in a 0.18um CMOS technology. The simulation results highly verify the effectiveness of the proposed structure. The third system describes the design technique for double-sampled wideband ΔΣ ADCs with shifted loop delays (SLD). The added loop delay in the feedback branch relaxes the critical timing for DEM logic. Delay shifting can be combined with such useful techniques as low-distortion circuitry and noise coupling for wideband ΔΣ modulators. The presented techniques relax the timing for inherent quantization delay, reduce the speed requirements for the critical circuit blocks, and achieve power efficiency by replacing the power-hungry blocks normally used in the modulators. Analysis of all architectures allows the choice of the most power-efficient topology for a wideband ΔΣ modulator. The proposed second-order and third-order ΔΣ modulators were designed and simulated to verify the effectiveness of the shifted loop delays techniques.Keywords: Noise-shaping, Shifted Loop Delays, Delta-Sigma Modulator, Low-distortion, AD

Design of low OSR, high precision analog-to-digital converters

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.Keywords: Delta-Sigma, Loop Filter, Oversampled ADC, Gain Stage, Pipeline, Noise Shapin

Simulation, and Overload and Stability Analysis of Continuous Time Sigma Delta Modulator

The ever increasing demand for faster and more powerful digital applications requires high speed, high resolution ADCs. Currently, sigma delta modulators ADCs are extensively used in broadband telecommunication systems because they are an effective solution for high data-rate wireless communication systems that require low power consumption, high speed, high resolution, and large signal bandwidths. Because mixed-signal integrated circuits such as Continuous Time sigma delta modulators contain both analog and digital circuits, mixed signal circuits are not as simple to model and simulate as all discrete or all analog systems. In this dissertation, the delta transform is used to simulate CT sigma delta modulators, and its speed and accuracy are compared to the other methods. The delta transform method is shown to be a very simple and effective method to get accurate results at reasonable speeds when compared with several existing simulation methods. When a CT sigma delta modulator is overloaded, sigma delta modulator\u27s output signal to quantization noise ratio (SQNR) decreases when the sigma delta modulator\u27s input is increased over a certain value. In this dissertation, the range of quantizer gains that cause overload are determined and the values ware used to determine the input signal power that prevents overload and the CT sigma delta modulator\u27s maximum SQNR. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that prevents overload and the maximum SQNR. Determining the stability criteria for CT sigma delta modulators is more difficult than it is for Discrete time sigma delta modulators (DT sigma delta modulators) because CT sigma delta modulators include delays which are modeled mathematically by exponential functions for CT systems. In this dissertation an analytical root locus method is used to determine the stability criteria for CT sigma delta modulators. This root locus method determines the range of quantizer gains for which a CT sigma delta modulator is stable. These values can then be used to determine input signal and internal signal powers that prevent sigma delta modulators from becoming unstable. Also, the maximum input power that keeps the CT sigma delta modulators stable for CT sigma delta modulators operating in overload can be determined. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that keeps the CT sigma delta modulators stable

LOW-VOLTAGE LOW-POWER ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

On The Implementation of Input-Feedforward Delta–Sigma Modulators

Abstract—This brief addresses some practical issues on the implementation of the input-feedforward delta–sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed. Index Terms—Analog-to-digital, delta–sigma(16), input-feedforward, oversampling