A Predictable Communication Scheme for Embedded Multiprocessor Systems

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictability can be obtained statically or dynamically. A dynamic allocation is more suitable for flexible multiprocessor systems and requires the implementation of a Quality-of-Service (QoS) mechanism. This paper explores the main QoS schemes suitable for such systems: connection-oriented and connectionless. The simulation results show that the connectionless scheme provides a better predictability in terms of message latency with an acceptable buffer requirement. This work provides the designer with valuable guidelines to choose a priori the QoS parameters such that they can be confident on the predicted results

Performance modelling and high performance buffer design for the system with network on chip

High performance novel dynamically allocated multi-queue (DAMQ) buffer schemes forsystems with network on chip (NoC) have been proposed and evaluated in this dissertation. Ananalytical model to predict performance of a NoC where wormhole switching technique andfully adaptive routing protocols has been developed and compared with simulations.In this dissertation, a novel analytical model for NoC which makes use of simple closeform calculations is presented. This model provides accurate network performance prediction inthe network stable region. The validity of this model is demonstrated by comparing analyticalprediction with simulation results obtained on high-radix k-ary 2-cube networks.Three novel switch buffer schemes, DAMQall, DAMQmin and DAMQshared, for system onchip with an interconnection network are also reported. The proposed schemes are based on aDAMQ self-compacting buffer hardware design. These schemes outperform existing approaches.DAMQall have similar performance using only half of the buffer size used in traditional SAMQimplementations. DAMQmin provides an excellent approach to optimize buffer managementproviding a good throughput when the network has a larger load. DAMQshared scheme lets virtualchannels from different physical channel share free buffer space. While providing similarperformance, DAMQshared scheme uses only around sixty percent of the buffer size that is used intraditional implementation for NoCs. In addition, using same size buffers, DAMQsharedoutperforms existing approaches such as SAMQ and DAMQall by 1% to 2% in throughput. Theproposed schemes also make a better utilization of the available buffer space

A probabilistic approach to early communication performance estimation for electronic system-level design

Today\u27s embedded system designers face the challenges of ever increasing complexity and shorter time-to-market deadlines. System-level methodologies emerge to meet these challenges. Refinement-based methodologies, such as the SpecC methodology and Transaction Level Modeling, continue to gain popularity in the embedded system designers\u27 community. However, as more communication-dominated applications and architectures appear in the market, designers find that the lack of models allowing system-level communication analysis is a major limiting factor in current system-level design methodologies. Thus, modeling for system-level communication analysis is key for a design methodology to thrive with today\u27s embedded system designers. This work presents a new approach to system-level modeling that allows better communication analysis earlier in the design process. This approach defines a new model that utilizes random variables to include the communication details at higher abstraction levels. This work proposes a probabilistic model to include and evaluate the system communication features in the higher abstraction level. Guidelines to include the proposed model into a refinement-based methodology are presented, and methods for performance estimation are shown

On the impact of traffic statistics on quality of service for networks on chip

Abstract — Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. I