Developing a Mathematical Model for Bobbin Lace

Bobbin lace is a fibre art form in which intricate and delicate patterns are created by braiding together many threads. An overview of how bobbin lace is made is presented and illustrated with a simple, traditional bookmark design. Research on the topology of textiles and braid theory form a base for the current work and is briefly summarized. We define a new mathematical model that supports the enumeration and generation of bobbin lace patterns using an intelligent combinatorial search. Results of this new approach are presented and, by comparison to existing bobbin lace patterns, it is demonstrated that this model reveals new patterns that have never been seen before. Finally, we apply our new patterns to an original bookmark design and propose future areas for exploration.Comment: 20 pages, 18 figures, intended audience includes Artists as well as Computer Scientists and Mathematician

Completion and deficiency problems

Given a partial Steiner triple system (STS) of order $n$, what is the order of the smallest complete STS it can be embedded into? The study of this question goes back more than 40 years. In this paper we answer it for relatively sparse STSs, showing that given a partial STS of order $n$ with at most $r \le \varepsilon n^2$ triples, it can always be embedded into a complete STS of order $n+O(\sqrt{r})$, which is asymptotically optimal. We also obtain similar results for completions of Latin squares and other designs. This suggests a new, natural class of questions, called deficiency problems. Given a global spanning property $\mathcal{P}$ and a graph $G$, we define the deficiency of the graph $G$ with respect to the property $\mathcal{P}$ to be the smallest positive integer $t$ such that the join $G\ast K_t$ has property $\mathcal{P}$. To illustrate this concept we consider deficiency versions of some well-studied properties, such as having a $K_k$-decomposition, Hamiltonicity, having a triangle-factor and having a perfect matching in hypergraphs. The main goal of this paper is to propose a systematic study of these problems; thus several future research directions are also given

A Micro Power Hardware Fabric for Embedded Computing

Field Programmable Gate Arrays (FPGAs) mitigate many of the problemsencountered with the development of ASICs by offering flexibility, faster time-to-market, and amortized NRE costs, among other benefits. While FPGAs are increasingly being used for complex computational applications such as signal and image processing, networking, and cryptology, they are far from ideal for these tasks due to relatively high power consumption and silicon usage overheads compared to direct ASIC implementation. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. In this research, a parameterized, reconfigurable fabric model named as domain specific fabric (DSF) is developed that exhibits ASIC-like power characteristics for Digital Signal Processing (DSP) style applications. Using this model, the impact of varying different design parameters on power and performance has been studied. Different optimization techniques like local search and simulated annealing are used to determine the appropriate interconnect for a specific set of applications. A design space exploration tool has been developed to automate and generate a tailored architectural instance of the fabric.The fabric has been synthesized on 160 nm cell-based ASIC fabrication process from OKI and 130 nm from IBM. A detailed power-performance analysis has been completed using signal and image processing benchmarks from the MediaBench benchmark suite and elsewhere with comparisons to other hardware and software implementations. The optimized fabric implemented using the 130 nm process yields energy within 3X of a direct ASIC implementation, 330X better than a Virtex-II Pro FPGA and 2016X better than an Intel XScale processor

Watermarking FPGA Bitfile for Intellectual Property Protection

Intellectual property protection (IPP) of hardware designs is the most important requirement for many Field Programmable Gate Array (FPGA) intellectual property (IP) vendors. Digital watermarking has become an innovative technology for IPP in recent years. Existing watermarking techniques have successfully embedded watermark into IP cores. However, many of these techniques share two specific weaknesses: 1) They have extra overhead, and are likely to degrade performance of design; 2) vulnerability to removing attacks. We propose a novel watermarking technique to watermark FPGA bitfile for addressing these weaknesses. Experimental results and analysis show that the proposed technique incurs zero overhead and it is robust against removing attacks

A complete solution to the infinite Oberwolfach problem

Let $F$ be a $2$-regular graph of order $v$. The Oberwolfach problem, $OP(F)$, asks for a $2$-factorization of the complete graph on $v$ vertices in which each $2$-factor is isomorphic to $F$. In this paper, we give a complete solution to the Oberwolfach problem over infinite complete graphs, proving the existence of solutions that are regular under the action of a given involution free group $G$. We will also consider the same problem in the more general contest of graphs $F$ that are spanning subgraphs of an infinite complete graph $\mathbb{K}$ and we provide a solution when $F$ is locally finite. Moreover, we characterize the infinite subgraphs $L$ of $F$ such that there exists a solution to $OP(F)$ containing a solution to $OP(L)$