Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines

MINIMALIST is a new extensible environment for the synthesis and verification of burst-mode asynchronous finite-state machines. MINIMALIST embodies a complete technology-independent synthesis path, with state-of-the-art exact and heuristic asynchronous synthesis algorithms, e.g.optimal state assignment (CHASM), two-level hazard-free logic minimization (HFMIN, ESPRESSO-HF, and IMPYMIN), and synthesis-for-testability. Unlike other asynchronous synthesis packages, MINIMALIST also offers many options:literal vs. product optimization, single- vs. multi-output logic minimization, using vs. not using fed-back outputs as state variables, and exploring varied code lengths during state assignment, thus allowing the designer to explore trade-offs and select the implementation style which best suits the application. MINIMALIST benchmark results demonstrate its ability to produce implementations with an average of 34% and up to 48% less area, and an average of 11% and up to 37% better performance, than the best existing package. Our synthesis-for-testability method guarantees 100% testability under both stuck-at and robust path delay fault models,requiring little or no overhead. MINIMALIST also features both command-line and graphic user interfaces, and supports extension via well-defined interfaces for adding new tools. As such, it is easily augmented to form a complete path to technology-dependent logic

Custom Integrated Circuits

Contains reports on ten research projects.Analog Devices, Inc.IBM CorporationNational Science Foundation/Defense Advanced Research Projects Agency Grant MIP 88-14612Analog Devices Career Development Assistant ProfessorshipU.S. Navy - Office of Naval Research Contract N0014-87-K-0825AT&TDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

A partial scan methodology for testing self-timed circuits

technical reportThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable

Experimental and simulation study on the effect of geometrical and flow parameters for combined-hole film cooling

Film cooling method was applied to the turbine blades to provide thermal protection from high turbine inlet temperatures in modern gas turbines. Recent literature discovers that combining two cylindrical holes of film cooling is one of the ways to further enhance the film cooling performances. In the present study, a batch of simulations and experiments involving two cylindrical holes with opposite compound angle were carried out and this two cylindrical hole also known as combined-hole film cooling. The main objective of this study is to determine the influence of different blowing ratio, M with a combination of different lateral distance between cooling holes (PoD), a streamwise distance between cooling holes (LoD) and compound angle of cooling hole (1/2) on the film cooling performance. The simulation of the present study had been carried out by using Computational Fluid Dynamic (CFD) with application of Shear Stress Transport (SST) turbulence model analysis from ANSYS CFX. Meanwhile, the experimental approach makes used of open end wind tunnel and the temperature distributions were measured by using infrared thermography camera. The purpose of the experimental approach in the present study is to validate three cases from all cases considered in the simulation approach. As the results shown, the lateral coverage was observed to be increased as PoD and 1/2 increased due to the interaction between two cooling air ejected from both cooling holes. Meanwhile, film cooling performance insignificantly changed when different LoD was applied. As the conclusion, a combination of the different geometrical parameters with various flow parameters produced a pattern of results. Therefore, the best configuration has been determined based on the average area of film cooling effectiveness. For M = 0.5, PoD = 1.0, LoD = 2.5 and 1 / 2 = -45o /+45o case is the most effective configuration. In the case of M = 1.0 and M = 1.5, PoD = 0.0, LoD = 3.5, 1 / 2 = -45o /+45o and PoD = 0.0, LoD = 2.5, 1 / 2 = -45o /+30o are the best configurations based on the overall performance of film cooling

Ensuring a High Quality Digital Device through Design for Testability

An electronic device is reliable if it is available for use most of the times throughout its life. The reliability can be affected by mishandling and use under abnormal operating conditions. High quality product cannot be achieved without proper verification and testing during the product development cycle. If the design is difficult to test, then it is very likely that most of the faults will not be detected before it is shipped to the customer. This paper describes how product quality can be improved by making the hardware design testable. Various designs for testability techniqueswere discussed. A three bit counter circuit was used to illustrate the benefits of design for testability by using scan chain methodology