Development of Compute-in-Memory Memristive Crossbar Architecture with Composite Memory Cells

In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. Also, we define their applications e.g. digital/analog logic, memory, etc. along with their drawbacks and implementation limitations. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the next section of the chapter, 2M1M crossbar array performance to be utilized as memory platform is described and we conceived pure memristive 2M1M crossbar array maintains high density, energy efficiency and low read and write time in comparison with other state of art memory architectures. This chapter concluded that utilizing a composite memory cell based on non-volatile memristor devices allow a more efficient combination of processing and storage architectures (compute-in-memory) to overcome the memory wall problem and enhance the computational efficiency for beyond Von-Neumann computing platforms

Design of Resistive Synaptic Devices and Array Architectures for Neuromorphic Computing

abstract: Over the past few decades, the silicon complementary-metal-oxide-semiconductor (CMOS) technology has been greatly scaled down to achieve higher performance, density and lower power consumption. As the device dimension is approaching its fundamental physical limit, there is an increasing demand for exploration of emerging devices with distinct operating principles from conventional CMOS. In recent years, many efforts have been devoted in the research of next-generation emerging non-volatile memory (eNVM) technologies, such as resistive random access memory (RRAM) and phase change memory (PCM), to replace conventional digital memories (e.g. SRAM) for implementation of synapses in large-scale neuromorphic computing systems. Essentially being compact and “analog”, these eNVM devices in a crossbar array can compute vector-matrix multiplication in parallel, significantly speeding up the machine/deep learning algorithms. However, non-ideal eNVM device and array properties may hamper the learning accuracy. To quantify their impact, the sparse coding algorithm was used as a starting point, where the strategies to remedy the accuracy loss were proposed, and the circuit-level design trade-offs were also analyzed. At architecture level, the parallel “pseudo-crossbar” array to prevent the write disturbance issue was presented. The peripheral circuits to support various parallel array architectures were also designed. One key component is the read circuit that employs the principle of integrate-and-fire neuron model to convert the analog column current to digital output. However, the read circuit is not area-efficient, which was proposed to be replaced with a compact two-terminal oscillation neuron device that exhibits metal-insulator-transition phenomenon. To facilitate the design exploration, a circuit-level macro simulator “NeuroSim” was developed in C++ to estimate the area, latency, energy and leakage power of various neuromorphic architectures. NeuroSim provides a wide variety of design options at the circuit/device level. NeuroSim can be used alone or as a supporting module to provide circuit-level performance estimation in neural network algorithms. A 2-layer multilayer perceptron (MLP) simulator with integration of NeuroSim was demonstrated to evaluate both the learning accuracy and circuit-level performance metrics for the online learning and offline classification, as well as to study the impact of eNVM reliability issues such as data retention and write endurance on the learning performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Semiconductor Memory Applications in Radiation Environment, Hardware Security and Machine Learning System

abstract: Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications. In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level. Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well. Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm. Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Advanced photon counting applications with superconducting detectors

Superconducting nanowire single photon detectors (SNSPDs) have emerged as mature detection technology that offers superior performance relative to competing infrared photon counting technologies. SNSPDs have the potential to revolutionize a range of advanced infrared photon counting applications, from quantum information science to remote sensing. The scale up to large area SNSPD arrays or cameras consisting of hundreds or thousands of pixels is limited by efficient readout schemes. This thesis gives a full overview of current SNSPD technology, describing design, fabrication, testing and applications. Prototype 4-pixel SNSPD arrays (30 x 30 µm2 and 60 x 60 µm2) were fabricated, tested and time-division multiplexed via a power combiner. In addition, a photon-number resolved code-division multiplexed 4-pixel array was simulated. Finally, a 100 m calibration-free distributed fibre temperature testbed, based on Raman backscattered photons detected by a single pixel fibre-coupled SNSPD housed in a Gifford McMahon cryostat was experimentally demonstrated with a spatial resolution of approximately 83 cm. At present, it is the longest range distributed thermometer based on SNSPD sensing

Resistive Switching in Transition Metal Oxides for Integrated Non-volatile Memory

Transition metal oxides (TMOs) exhibit characteristic resistance changes when subjected to high electric fields due to the creation, drift and diffusion of defects, and this resistive-switching response is of interest for future non-volatile memory applications. Indeed, resistive random access memories (ReRAM) are considered promising alternatives to conventional charge storage-based devices because of their low production cost, simple fabrication, and excellent scalability. However, the realization of reliable ReRAM devices and their integration in large-scale arrays requires further understanding of the switching mechanisms and the development of new strategies for improving integrated device functionality. The aim of this work is to understand the role of the material structure on device reliability and to investigate the integration of passive selector elements with memory devices for use in memory cross-bar arrays. The thesis begins by investigating the properties of relevant oxide films (ALD HfO2 and plasma deposited NbOx) and then addresses three technologically relevant problems. Specifically these include: 1) understanding how the roughness of metal/dielectric interfaces affects dielectric breakdown and switching behaviour; 2) exploring methods for reducing the operating current of selector and memory/selector devices and 3) investigating the effect of operating conditions on the switching response of devices. The first of these studies is based on Pt/Ti/HfO2/Pt devices and combines experimental methods and finite element modelling to understand the effect of the Pt/HfO2 interface roughness on the electroforming and switching response. Atomic force microscopy (AFM) showed that the roughness of Pt electrodes deposited by electron-beam evaporation increased with film thickness due to facetted grain growth. Results show that roughness leads to a reduction in the electroforming voltage of HfO2, an increase in the failure rate of devices, and a corresponding reduction in resistive switching reliability. Conventional wisdom suggests that these effects result from local electric field enhancement in the vicinity of electrode asperities. However, the effect on electroforming voltage is much less than estimated from simple geometric considerations. Comparison with finite-element modelled showed high-aspect-ratio asperities can produce field enhancements of more than an order of magnitude but that the generation and redistribution of defects moderates this effect prior to dielectric breakdown. As a consequence, the effect of field enhancement is less than anticipated from the initial electric-field distribution alone. It is argued that the increase in the device failure rate with increasing electrode roughness derives partly from an increase in the film defect density and effective device area and that these effects contribute to the reduction in breakdown voltage. The second study showed that the leakage current in NbO2-x selector (1S) elements is shown to be reduced by the properties of an adjacent memory (1M) element when integrated into a hybrid selector-memory device structure. This is shown to result from current confinement in conductive filaments formed in the memory layer. Finite element modelling of the selector-memory structures is used to confirm the observations and to explore material dependencies. The thermal and electrical conductivities of the memory layer are shown to influence the threshold current, but the dominant effect is due to current confinement. The final study explores the effect of device operating conditions on its operation and identifies an alternative approach for reducing the forming and RESET current in integrated memory/selector devices. This study is based on Pt/Nb/HfO2/Pt devices which require a very "soft" electroforming process. Such devices are shown to undergo configurable switching controlled by the SET compliance current. When operated at a low compliance-current (~100 µA), devices show uniform bipolar resistive switching behaviour. As the compliance current is increased (~500 µA), the switching mode changes to integrated threshold-resistive (1S1M) switching, and at still higher currents (~1 mA), it changes to symmetric threshold switching (1S) characteristic of threshold switching in NbO2-. These switching transitions are shown to be consistent with the development of an NbO2- interlayer at the Nb/HfO2 interface that is limited by the set compliance current due to its effect on oxygen transport and local Joule heating. The proposed mechanism is supported by finite element modelling of the 1S1M response assuming the presence of such an interlayer. These findings help to understand role of interface reactions in controlling device performance and provide a means for the self-assembly of integrated 1S1M resistive random access memory structures