ICONA: Inter Cluster ONOS Network Application

Several Network Operating Systems (NOS) have been proposed in the last few years for Software Defined Networks; however, a few of them are currently offering the resiliency, scalability and high availability required for production environments. Open Networking Operating System (ONOS) is an open source NOS, designed to be reliable and to scale up to thousands of managed devices. It supports multiple concurrent instances (a cluster of controllers) with distributed data stores. A tight requirement of ONOS is that all instances must be close enough to have negligible communication delays, which means they are typically installed within a single datacenter or a LAN network. However in certain wide area network scenarios, this constraint may limit the speed of responsiveness of the controller toward network events like failures or congested links, an important requirement from the point of view of a Service Provider. This paper presents ICONA, a tool developed on top of ONOS and designed in order to extend ONOS capability in network scenarios where there are stringent requirements in term of control plane responsiveness. In particular the paper describes the architecture behind ICONA and provides some initial evaluation obtained on a preliminary version of the tool.Comment: Paper submitted to a conferenc

Fault Tolerant Adaptive Parallel and Distributed Simulation through Functional Replication

This paper presents FT-GAIA, a software-based fault-tolerant parallel and distributed simulation middleware. FT-GAIA has being designed to reliably handle Parallel And Distributed Simulation (PADS) models, which are needed to properly simulate and analyze complex systems arising in any kind of scientific or engineering field. PADS takes advantage of multiple execution units run in multicore processors, cluster of workstations or HPC systems. However, large computing systems, such as HPC systems that include hundreds of thousands of computing nodes, have to handle frequent failures of some components. To cope with this issue, FT-GAIA transparently replicates simulation entities and distributes them on multiple execution nodes. This allows the simulation to tolerate crash-failures of computing nodes. Moreover, FT-GAIA offers some protection against Byzantine failures, since interaction messages among the simulated entities are replicated as well, so that the receiving entity can identify and discard corrupted messages. Results from an analytical model and from an experimental evaluation show that FT-GAIA provides a high degree of fault tolerance, at the cost of a moderate increase in the computational load of the execution units.Comment: arXiv admin note: substantial text overlap with arXiv:1606.0731

Cell replication and redundancy elimination during placement for cycle time optimization

This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques

Fault-Tolerant Adaptive Parallel and Distributed Simulation

Discrete Event Simulation is a widely used technique that is used to model and analyze complex systems in many fields of science and engineering. The increasingly large size of simulation models poses a serious computational challenge, since the time needed to run a simulation can be prohibitively large. For this reason, Parallel and Distributes Simulation techniques have been proposed to take advantage of multiple execution units which are found in multicore processors, cluster of workstations or HPC systems. The current generation of HPC systems includes hundreds of thousands of computing nodes and a vast amount of ancillary components. Despite improvements in manufacturing processes, failures of some components are frequent, and the situation will get worse as larger systems are built. In this paper we describe FT-GAIA, a software-based fault-tolerant extension of the GAIA/ART\`IS parallel simulation middleware. FT-GAIA transparently replicates simulation entities and distributes them on multiple execution nodes. This allows the simulation to tolerate crash-failures of computing nodes; furthermore, FT-GAIA offers some protection against byzantine failures since synchronization messages are replicated as well, so that the receiving entity can identify and discard corrupted messages. We provide an experimental evaluation of FT-GAIA on a running prototype. Results show that a high degree of fault tolerance can be achieved, at the cost of a moderate increase in the computational load of the execution units.Comment: Proceedings of the IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT 2016

A high-precision current-mode WTA-MAX circuit with multichip capability

This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented

A Resource Intensive Traffic-Aware Scheme for Cluster-based Energy Conservation in Wireless Devices

Wireless traffic that is destined for a certain device in a network, can be exploited in order to minimize the availability and delay trade-offs, and mitigate the Energy consumption. The Energy Conservation (EC) mechanism can be node-centric by considering the traversed nodal traffic in order to prolong the network lifetime. This work describes a quantitative traffic-based approach where a clustered Sleep-Proxy mechanism takes place in order to enable each node to sleep according to the time duration of the active traffic that each node expects and experiences. Sleep-proxies within the clusters are created according to pairwise active-time comparison, where each node expects during the active periods, a requested traffic. For resource availability and recovery purposes, the caching mechanism takes place in case where the node for which the traffic is destined is not available. The proposed scheme uses Role-based nodes which are assigned to manipulate the traffic in a cluster, through the time-oriented backward difference traffic evaluation scheme. Simulation study is carried out for the proposed backward estimation scheme and the effectiveness of the end-to-end EC mechanism taking into account a number of metrics and measures for the effects while incrementing the sleep time duration under the proposed framework. Comparative simulation results show that the proposed scheme could be applied to infrastructure-less systems, providing energy-efficient resource exchange with significant minimization in the power consumption of each device.Comment: 6 pages, 8 figures, To appear in the proceedings of IEEE 14th International Conference on High Performance Computing and Communications (HPCC-2012) of the Third International Workshop on Wireless Networks and Multimedia (WNM-2012), 25-27 June 2012, Liverpool, U

OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING

Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packagestwo-way partitioning, multi-way partitioning, recursive partitioning, flat partitioning, critical path, cutting cones, bottom-up clusters, top-down min-cut