4 research outputs found
An efficient Fault Localization Algorithm for IP/WDM Networks
We propose an algorithm for localizing multiple failures in an IP/WDM network. They can be either hard failures (unexpected events that interrupt suddenly the established channels) or soft failures (events that progressively degrade the quality of transmission). Hard failures are detected at the WDM layer, whereas soft failures can be detected at the optical layer if proper testing equipment is deployed, and/or by performance monitoring at a higher layer, which is here IP. The algorithm also tolerates missing and false alarms. Even without missing and false alarms, multiple fault localization is NP-hard. The diagnosis phase (i.e., the localization of the faulty components upon reception of the alarms) can however remain very fast, but at the expense of a very complex precomputation phase, carried out whenever the optical channels are set up or cleared down. We show how the algorithm performs on an example of an IP/WDM network
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Resource Contention in Real-time Systems
The divide—and—conquer method is extensively used for system design. For real-time systems the separated components execute concurrently using some common computational infrastructure and this can lead to contention for system resources, such as processors, memory, communication channels, and so on. Unless the resource contention is accommodated, then a system built from the composition of components may not function as expected and the “proven” behaviour of the components can be invalid. To overcome this uncertainty a divide—conquer—and—system-composition method is required. This thesis takes a different approach to many of the existing notations which focus on descriptions of behaviour. The Composite Transition System notation and algebra presented here enables the resource usage of the components to be specified and combined to form a composite system of concurrently executing components. By relating the composite system to the realisable behaviour of the system resources provided by the common infrastructure it becomes possible to determine any violation of the constraints imposed by the system resources. If the composite system model is then constrained by the resource behaviours then it is possible through an extraction operation to determine the modified behaviour of the components that will yield a system free of resource contention. Component specification, concurrent composition, the application of system level constraints and extraction are applied in this thesis to a system encountered in a commercial application. The purpose of this example is to demonstrate contention modelling and the mathematics of the notation, rather than to prove any specific properties of the application. Deployment of the notation to more complex applications will require the development of software tools to compute concurrent composition and extraction, and this is the motivation for the mathematical treatment in this thesis
OPTIMIZATION OF TEST/DIAGNOSIS/REWORK LOCATION(S) AND CHARACTERISTICS IN ELECTRONIC SYSTEMS ASSEMBLY
ABSTRACT
Title of Dissertation: OPTIMIZATION OF TEST/DIAGNOSIS/REWORK LOCATION(S) AND CHARACTERISTICS IN ELECTRONIC SYSTEMS ASSEMBLY
Zhen Shi, Doctor of Philosophy, 2004
Dissertation directed by: Associate Professor Peter A. Sandborn
Department of Mechanical Engineering
For electronic systems it is not uncommon for 60% or more of the recurring cost to be associated with testing. Performing tradeoffs associated with where in a process to test and what level of test, diagnosis and rework to perform are key to optimizing the cost and yield of an electronic system's assembly. In this dissertation, a methodology that uses a real-coded genetic algorithm has been developed to minimize the yielded cost of electronic products by optimizing the locations of test, diagnosis and rework operations and their characteristics.
This dissertation presents a test, diagnosis, and rework analysis model for use in electronic systems assembly. The approach includes a model of functional test operations characterized by fault coverage, false positives, and defects introduced in test; in addition, rework and diagnosis operations (diagnostic test) have variable success rates and their own defect introduction mechanisms. The model accommodates multiple rework attempts on a product instance. For use in practical assembly processes, the model has been extended by defining a general form of the relationship between test cost and fault coverage.
The model is applied within a framework for optimizing the location(s) and characteristics (fault coverage/test cost and rework attempts) of Test/Diagnosis/Rework (TDR) operations in a general assembly process. A new search algorithm called Waiting Sequence Search (WSS) is applied to traverse a general process flow to perform the cumulative calculation of a yielded cost objective function. Real-Coded Genetic Algorithms (RCGAs) are used to perform a multi-variable optimization that minimizes yielded cost. Several simple cases are analyzed for validation and general complex process flows are used to demonstrate the applicability of the algorithm. A real multichip module (MCM) manufacturing and assembly process is used to demonstrate that the optimization methodology developed in this dissertation can find test and rework solutions that have lower yielded cost than solutions calculated by manually choosing the test strategies and characteristics. The optimization methodology with Monte Carlo methods included for the process flow under uncertain inputs is also addressed in this dissertation.
It is anticipated that this research will improve the ability of manufacturing engineers to place TDR operations in a process flow. The ability to optimize the TDR operations can also be used as a feedback to a Design for Test (DFT) analysis of the electronic systems showing which portion of the system should be redesigned to accommodate testing for a higher level of fault coverage, and where there is less need for test