Radix-2n serial–serial multipliers

All serial–serial multiplication structures previously reported in the literature have been confined to bit serial–serial multipliers. An architecture for digit serial–serial multipliers is presented. A set of designs are derived from the radix-2n design procedure, which was first reported by the authors for the design of bit level pipelined digit serial–parallel structures. One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade-off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also, an area-efficient digit serial–serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are remapped to other cells, which make them redundant. The new designs have been implemented on the S40BG256 device from the SPARTAN family to prove functionality and assess performance

Improvements in CO2 Booster Architectures with Different Economizer Arrangements.

CO2 transcritical booster architectures are widely analyzed to be applied in centralized commercial refrigeration plants in consonance with the irrevocable phase-out of HFCs. Most of these analyses show the limitations of CO2 cycles in terms of energy e ciency, especially in warm countries. From the literature, several improvements have been proposed to raise the booster e ciency in high ambient temperatures. The use of economizers is an interesting technique to reduce the temperature after the gas cooler and to improve the energy e ciency of transcritical CO2 cycles. The economizer cools down the high pressure’s line of CO2 by evaporating the same refrigerant extracted from another point of the facility. Depending on the extraction point, some configurations are possible. In this work, di erent booster architectures with economizers have been analyzed and compared. From the results, the combination of the economizer with the additional compressor allows obtaining energy savings of up to 8.5% in warm countries and up to 4% in cold countries with regard to the flash-by-pass arrangement and reduce the volumetric displacement required of the MT compressors by up to 37%

Performance evaluation of high speed compressors for high speed multipliers

This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25°C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only

Review of experimental research on supercritical and transcritical thermodynamic cycles designed for heat recovery application

Supercritical operation is considered a main technique to achieve higher cycle efficiency in various thermodynamic systems. The present paper is a review of experimental investigations on supercritical operation considering both heat-to-upgraded heat and heat-to-power systems. Experimental works are reported and subsequently analyzed. Main findings can be summarized as: steam Rankine cycles does not show much studies in the literature, transcritical organic Rankine cycles are intensely investigated and few plants are already online, carbon dioxide is considered as a promising fluid for closed Brayton and Rankine cycles but its unique properties call for a new thinking in designing cycle components. Transcritical heat pumps are extensively used in domestic and industrial applications, but supercritical heat pumps with a working fluid other than CO2 are scarce. To increase the adoption rate of supercritical thermodynamic systems further research is needed on the heat transfer behavior and the optimal design of compressors and expanders with special attention to the mechanical integrity

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper utilizes a new 4 * 4 reversible gate called TSG gate to build the components of a primitive reversible/quantum ALU. The most significant aspect of the TSG gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. A Novel reversible 4:2 compressor is also designed from the TSG gate which is later used to design a novel 8x8 reversible Wallace tree multiplier. It is proved that the adder, 4:2 compressor and multiplier architectures designed using the TSG gate are better than their counterparts available in literature, in terms of number of reversible gates and garbage outputs. This is perhaps, the first attempt to design a reversible 4:2 compressor and a reversible Wallace tree multiplier as far as existing literature and our knowledge is concerned. Thus, this paper provides an initial threshold to build more complex systems which can execute complicated operations using reversible logic.Comment: 5 Pages; Published in Proceedings of the Fifth IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005), Bangkok, Thailand, 6-9 December 2005,pp.1425-142

Design and Implementation of a Lossless Serial High-Speed Data Compression System

The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the X-Match algorithm. This design involves important trade off that affects the compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware. This device typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbits/s data networks and storage applications where it can double the performance of the original systems. To get high compression rate or to get high data rate of communication not restriction to follow the parallel architecture of data compression. By using existing method the main draw backs are 1. Variation in compression 2. Throughput, 3.Latency, 4.High space, 5. High power. So by using this proposed method we can reduce the variation in the compression, latency and increase through put. And this novel VLSI architecture has a power consumption of 81mwatts powe