2,130 research outputs found
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Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques
The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware
Power efficient, event driven data acquisition and processing using asynchronous techniques
PhD ThesisData acquisition systems used in remote environmental monitoring equipment and biological
sensor nodes rely on limited energy supply soured from either energy harvesters or battery to
perform their functions. Among the building blocks of these systems are power hungry Analogue
to Digital Converters and Digital Signal Processors which acquire and process samples
at predetermined rates regardless of the monitored signal’s behavior. In this work we investigate
power efficient event driven data acquisition and processing techniques by implementing
an asynchronous ADC and an event driven power gated Finite Impulse Response (FIR) filter.
We present an event driven single slope ADC capable of generating asynchronous digital samples
based on the input signal’s rate of change. It utilizes a rate of change detection circuit
known as the slope detector to determine at what point the input signal is to be sampled. After
a sample has been obtained it’s absolute voltage value is time encoded and passed on to a Time
to Digital Converter (TDC) as part of a pulse stream. The resulting digital samples generated
by the TDC are produced at a rate that exhibits the same rate of change profile as that of the
input signal. The ADC is realized in 0.35mm CMOS process, covers a silicon area of 340mm
by 218mm and consumes power based on the input signal’s frequency.
The samples from the ADC are asynchronous in nature and exhibit random time periods between
adjacent samples. In order to process such asynchronous samples we present a FIR filter that is
able to successfully operate on the samples and produce the desired result. The filter also poses
the ability to turn itself off in-between samples that have longer sample periods in effect saving
power in the process
Continuous-time acquisition of biosignals using a charge-based ADC topology
This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion
A Low Energy FPGA Platform for Real-Time Event-Based Control
We present a wireless sensor node suitable for event-based real-time control networks. The node achieves low-power operation thanks to tight clock synchronisation with the network master (at present we refer to a star network but extensions are envisaged). Also, the node does not employ any programmable device but rather an FPGA, thus being inherently immune to attacks based on code tampering. Experimental results on a simple laboratory apparatus are presented
A 97 fJ/Conversion Neuron-ADC with Reconfigurable Sampling and Static Power Reduction
A bio-inspired Neuron-ADC with reconfigurable sampling and static power
reduction for biomedical applications is proposed in this work. The Neuron-ADC
leverages level-crossing sampling and a bio-inspired refractory circuit to
compressively converts bio-signal to digital spikes and
information-of-interest. The proposed design can not only avoid dissipating ADC
energy on unnecessary data but also achieve reconfigurable sampling, making it
appropriate for either low power operation or high accuracy conversion when
dealing with various kinds of bio-signals. Moreover, the proposed dynamic
comparator can reduce static power up to 41.1% when tested with a 10 kHz
sinusoidal input. Simulation results of 40 nm CMOS process show that the
Neuron-ADC achieves a maximum ENOB of 6.9 bits with a corresponding FoM of 97
fJ/conversion under 0.6 V supply voltage.Comment: Accepted to 2022 IEEE the 18th Asia Pacific Conference on Circuits
and Systems (APCCAS
An Error-Based Approximation Sensing Circuit for Event-Triggered, Low Power Wearable Sensors
Event-based sensors have the potential to optimize energy consumption at
every stage in the signal processing pipeline, including data acquisition,
transmission, processing and storage. However, almost all state-of-the-art
systems are still built upon the classical Nyquist-based periodic signal
acquisition. In this work, we design and validate the Polygonal Approximation
Sampler (PAS), a novel circuit to implement a general-purpose event-based
sampler using a polygonal approximation algorithm as the underlying sampling
trigger. The circuit can be dynamically reconfigured to produce a coarse or a
detailed reconstruction of the analog input, by adjusting the error threshold
of the approximation. The proposed circuit is designed at the Register Transfer
Level and processes each input sample received from the ADC in a single clock
cycle. The PAS has been tested with three different types of archetypal signals
captured by wearable devices (electrocardiogram, accelerometer and respiration
data) and compared with a standard periodic ADC. These tests show that
single-channel signals, with slow variations and constant segments (like the
used single-lead ECG and the respiration signals) take great advantage from the
used sampling technique, reducing the amount of data used up to 99% without
significant performance degradation. At the same time, multi-channel signals
(like the six-dimensional accelerometer signal) can still benefit from the
designed circuit, achieving a reduction factor up to 80% with minor performance
degradation. These results open the door to new types of wearable sensors with
reduced size and higher battery lifetime
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Design and Optimization of Low-power Level-crossing ADCs
This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit
High-resolution distributed sampling of bandlimited fields with low-precision sensors
The problem of sampling a discrete-time sequence of spatially bandlimited
fields with a bounded dynamic range, in a distributed,
communication-constrained, processing environment is addressed. A central unit,
having access to the data gathered by a dense network of fixed-precision
sensors, operating under stringent inter-node communication constraints, is
required to reconstruct the field snapshots to maximum accuracy. Both
deterministic and stochastic field models are considered. For stochastic
fields, results are established in the almost-sure sense. The feasibility of
having a flexible tradeoff between the oversampling rate (sensor density) and
the analog-to-digital converter (ADC) precision, while achieving an exponential
accuracy in the number of bits per Nyquist-interval per snapshot is
demonstrated. This exposes an underlying ``conservation of bits'' principle:
the bit-budget per Nyquist-interval per snapshot (the rate) can be distributed
along the amplitude axis (sensor-precision) and space (sensor density) in an
almost arbitrary discrete-valued manner, while retaining the same (exponential)
distortion-rate characteristics. Achievable information scaling laws for field
reconstruction over a bounded region are also derived: With N one-bit sensors
per Nyquist-interval, Nyquist-intervals, and total network
bitrate (per-sensor bitrate ), the maximum pointwise distortion goes to zero as
or . This is shown to be possible
with only nearest-neighbor communication, distributed coding, and appropriate
interpolation algorithms. For a fixed, nonzero target distortion, the number of
fixed-precision sensors and the network rate needed is always finite.Comment: 17 pages, 6 figures; paper withdrawn from IEEE Transactions on Signal
Processing and re-submitted to the IEEE Transactions on Information Theor
A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers
The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply
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