New method to design multiplier-less pulse shaping filters with minimal number of operations

Software-Defined Radio (SDR) technology is evolving rapidly, offering higher flexibility for wireless communication networks. For the sake of performance, and power consumption, filtering is commonly implemented in hardware using FPGAs. Pulse shaping in the transmitter and the corresponding matched filtering in the receiver, which together satisfy the Nyquist inter symbol interference (ISI) criterion, are no exception to this. To decrease the FPGA resources used by filters, to increase speed and to decrease power consumption the filter coefficients can be optimized by expressing them in canonical signed digit (CSD) form, using as few arithmetic operations per filter as possible, while maintaining acceptable filter characteristics. In this paper a new method to decrease the number of nonzero signed digits is presented. With this method a reduction of up to 65% of the nonzero signed digits per filter is realized, while decreasing the ISI ratio too