A Simulation Analysis of Constrained Rate and Line Assembly Processes

Simulation presents a way to analyze the performance of a system with zone capacity constraints, operator constraints, and precedence constraints in an assembly line using takt analysis. A small-scale model of an aircraft assembly line is built in Simio and precedence constraints are modified in independent simulations. The primary performance metric is traveled work, for which a definition is given. A method of calculating traveled work is presented, as well as an interpretation that states the effect on throughput. These results show that, ceteris paribus, traveled work increases flowtime, which decreases throughput. Modifications to the system are suggested that can reduce traveled work

Domain-Specific Computing Architectures and Paradigms

We live in an exciting era where artificial intelligence (AI) is fundamentally shifting the dynamics of industries and businesses around the world. AI algorithms such as deep learning (DL) have drastically advanced the state-of-the-art cognition and learning capabilities. However, the power of modern AI algorithms can only be enabled if the underlying domain-specific computing hardware can deliver orders of magnitude more performance and energy efficiency. This work focuses on this goal and explores three parts of the domain-specific computing acceleration problem; encapsulating specialized hardware and software architectures and paradigms that support the ever-growing processing demand of modern AI applications from the edge to the cloud. This first part of this work investigates the optimizations of a sparse spatio-temporal (ST) cognitive system-on-a-chip (SoC). This design extracts ST features from videos and leverages sparse inference and kernel compression to efficiently perform action classification and motion tracking. The second part of this work explores the significance of dataflows and reduction mechanisms for sparse deep neural network (DNN) acceleration. This design features a dynamic, look-ahead index matching unit in hardware to efficiently discover fine-grained parallelism, achieving high energy efficiency and low control complexity for a wide variety of DNN layers. Lastly, this work expands the scope to real-time machine learning (RTML) acceleration. A new high-level architecture modeling framework is proposed. Specifically, this framework consists of a set of high-performance RTML-specific architecture design templates, and a Python-based high-level modeling and compiler tool chain for efficient cross-stack architecture design and exploration.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162870/1/lchingen_1.pd

Deep Reinforcement Learning for Vehicular Edge Computing: An Intelligent Offloading System

The development of smart vehicles brings drivers and passengers a comfortable and safe environment. Various emerging applications are promising to enrich users' traveling experiences and daily life. However, how to execute computing-intensive applications on resource-constrained vehicles still faces huge challenges. In this article, we construct an intelligent offloading system for vehicular edge computing by leveraging deep reinforcement learning. First, both the communication and computation states are modelled by finite Markov chains. Moreover, the task scheduling and resource allocation strategy is formulated as a joint optimization problem to maximize users' Quality of Experience (QoE). Due to its complexity, the original problem is further divided into two sub-optimization problems. A two-sided matching scheme and a deep reinforcement learning approach are developed to schedule offloading requests and allocate network resources, respectively. Performance evaluations illustrate the effectiveness and superiority of our constructed system

A Simulation Analysis of Constrained Rate and Line Assembly Processes

Simulation presents a way to analyze the performance of a system with zone capacity constraints, operator constraints, and precedence constraints in an assembly line using takt analysis. A small-scale model of an aircraft assembly line is built in Simio and precedence constraints are modified in independent simulations. The primary performance metric is traveled work, for which a definition is given. A method of calculating traveled work is presented, as well as an interpretation that states the effect on throughput. These results show that, ceteris paribus, traveled work increases flowtime, which decreases throughput. Modifications to the system are suggested that can reduce traveled work

A hybrid algorithm for the integrated production planning in the pulp and paper industry

Tese de mestrado integrado. Engenharia Industrial e Gestão. Faculdade de Engenharia. Universidade do Porto. 201