Network Traffic Control Design and Evaluation

Recently, the term bufferbloat has been coined to indicate the uncontrolled growth of the network queueing time. A number of network traffic control strategies have been proposed to control network queueing delay. Active Queue Management (AQM) algorithms such as RED, CoDel and PIE have been proposed to drop packets before the network queues become full and to notify upper layers, e.g., transport protocols, about possible congestion status. Innovative packet schedulers such as FQ-CoDel, have been introduced to prioritize flows which do not build queues. Strategies to reduce device buffering, e.g., BQL, have been proposed to increase the effectiveness of packet schedulers. Network experimentation through simulators such as ns-3, one of the most used network simulators, allows the study of bufferbloat and to evaluate solutions in a controlled environment. In this work, we aligned the ns-3 queueing system to the Linux one, one of the most used networking stacks. We introduced in ns-3 a traffic control module modelled after the Linux one. Our design allowed the introduction in ns-3 of schedulers such as FQ-CoDel and of algorithms to dynamically size the buffers such as BQL. Also, we devised a new emulation methodology to overcome some limitations and increase the emulation fidelity. Then, by using the new emulation methodology, we validated the traffic control module with its AQM algorithms (RED, CoDel, FQ-CoDel and PIE). Our experiments prove the high fidelity of network emulation and the high accuracy of the traffic control module and AQM algorithms. Then, we show two proposals of design and evaluation of traffic control strategies by using ns-3. Firstly, we designed and evaluated a traffic control layer for the backlog management in 3GPP stacks. The approach improves significantly the flows performance in LTE networks. Secondly, we highlighted possible design flaws in rate based AQM algorithms and proposed an alternative flow control approach. The approach allows the improvement of the effectiveness of AQM algorithms. Our work will allow researchers to design and evaluate in a more accurate manner traffic control strategies through ns-3 based simulation and emulation and to evaluate the accuracy of other modules implemented in ns-3

MGSim - Simulation tools for multi-core processor architectures

MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.Comment: 33 pages, 22 figures, 4 listings, 2 table

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a 7-stage pipeline, fully bypassed, microprocessor running the MIPS-III ISA, a 4-stage input-buffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler toolchain to assist in developing software for Heracles

SplitFS: Reducing Software Overhead in File Systems for Persistent Memory

We present SplitFS, a file system for persistent memory (PM) that reduces software overhead significantly compared to state-of-the-art PM file systems. SplitFS presents a novel split of responsibilities between a user-space library file system and an existing kernel PM file system. The user-space library file system handles data operations by intercepting POSIX calls, memory-mapping the underlying file, and serving the read and overwrites using processor loads and stores. Metadata operations are handled by the kernel PM file system (ext4 DAX). SplitFS introduces a new primitive termed relink to efficiently support file appends and atomic data operations. SplitFS provides three consistency modes, which different applications can choose from, without interfering with each other. SplitFS reduces software overhead by up-to 4x compared to the NOVA PM file system, and 17x compared to ext4-DAX. On a number of micro-benchmarks and applications such as the LevelDB key-value store running the YCSB benchmark, SplitFS increases application performance by up to 2x compared to ext4 DAX and NOVA while providing similar consistency guarantees

Hierarchical Content Stores in High-speed ICN Routers: Emulation and Prototype Implementation

Recent work motivates the design of Information-centric rou-ters that make use of hierarchies of memory to jointly scale in the size and speed of content stores. The present paper advances this understanding by (i) instantiating a general purpose two-layer packet-level caching system, (ii) investigating the solution design space via emulation, and (iii) introducing a proof-of-concept prototype. The emulation-based study reveals insights about the broad design space, the expected impact of workload, and gains due to multi-threaded execution. The full-blown system prototype experimentally confirms that, by exploiting both DRAM and SSD memory technologies, ICN routers can sustain cache operations in excess of 10Gbps running on off-the-shelf hardware