Simplifying data path processing in next-generation routers

ABSTRACT Customizable packet processing is an important aspect of next-generation networks. Packet processing architectures using multi-core systems on a chip can be difficult to program. In our work, we propose a new packet processor design that simplifies packet processing by managing packet contexts in hardware. We show how such a design scales to large systems. Our results also show that the management of such a system is feasible with the proposed mapping algorithm

Network application driven instruction set extensions for embedded processing clusters

Grunewald M, Le DK, Kastens U, et al. Network application driven instruction set extensions for embedded processing clusters. In: IEEE Computer Society. Technical Committee on Parallel Processing, Technische Universität Dresden. Technical Committee on Parallel Processing, eds. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. Los Alamitos, Calif. : IEEE Comput. Soc; 2004: 209-214.This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processorýs instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly