Adaptive multilevel quadrature amplitude radio implementation in programmable logic

Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more “robust” physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in “burst” mode, and can reliably synchronize to different QAM constellations “burst-by-burst”. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers

High-performance signal acquisition algorithms for wireless communications receivers

Due to the uncertainties introduced by the propagation channel, and RF and mixed signal circuits imperfections, digital communication receivers require efficient and robust signal acquisition algorithms for timing and carrier recovery, and interfer- ence rejection. The main theme of this work is the development of efficient and robust signal synchronization and interference rejection schemes for narrowband, wideband and ultra wideband communications systems. A series of novel signal acquisition schemes together with their performance analysis and comparisons with existing state-of-the- art results are introduced. The design effort is first focused on narrowband systems, and then on wideband and ultra wideband systems. For single carrier modulated narrowband systems, it is found that conventional timing recovery schemes present low efficiency, e.g., certain feedback timing recov- ery schemes exhibit the so-called hang-up phenomenon, while another class of blind feedforward timing recovery schemes presents large self-noise. Based on a general re- search framework, we propose new anti-hangup algorithms and prefiltering techniques to speed up the feedback timing recovery and reduce the self-noise of feedforward tim- ing estimators, respectively. Orthogonal frequency division multiplexing (OFDM) technique is well suited for wideband wireless systems. However, OFDM receivers require high performance car-rier and timing synchronization. A new coarse synchronization scheme is proposed for efficient carrier frequency offset and timing acquisition. Also, a novel highly accurate decision-directed algorithm is proposed to track and compensate the residual phase and timing errors after the coarse synchronization step. Both theoretical analysis and computer simulations indicate that the proposed algorithms greatly improve the performance of OFDM receivers. The results of an in-depth study show that a narrowband interference (NBI) could cause serious performance loss in multiband OFDMbased ultra-wideband (UWB) sys- tems. A novel NBI mitigation scheme, based on a digital NBI detector and adaptive analog notch filter bank, is proposed to reduce the effects of NBI in UWB systems. Simulation results show that the proposed NBI mitigation scheme improves signifi- cantly the performance of a standard UWB receiver (this improvement manifests as a signal-to-noise ratio (SNR) gain of 9 dB)

Nuevas implementaciones digitales de sincronismos de BIT y portadora en Módem CPM

Las técnicas digitales aplicadas a receptores y transmisores están imponiéndose a las convencionales técnicas analógicas por las diversas ventajas que supone. En este sentido se impone una investigación con el fin de desarrollar dichas técnicas o mejorarlas en algún aspecto. La idea principal que engloba esta Tesis Doctoral es precisamente la indagación en algunas de dichas técnicas, su análisis, caracterización y aplicación a dos casos concretos. En un primer momento se han caracterizado dos canales de comunicaciones donde se pretende hacer uso de las técnicas a desarrollar. Este es un aspecto importante para conocer las condiciones reales en que deberán operar los algoritmos y cómo pueden verse afectados. Los canales que se caracterizan corresponden al establecido para satélites de órbita baja y el formado por las líneas de distribución de media tensión. En segundo lugar se ha realizado una descripción del tipo de modulación que se pretende emplear en los canales (GMSK) y se ha tratado de obtener una estructura del receptor con la menor complejidad posible. Basándose en una descripción de la modulación mediante una aproximación que da lugar a un modelo lineal, se desarrolla un receptor lineal de estructura sencilla y con unas prestaciones razonables, suponiendo una gran ventaja. Una vez descrita la estructura del receptor en el cual se van a emplear los algoritmos, se tratan dos aspectos cruciales en los receptores: la sincronización de portadora y el sincronismo de bit. Las técnicas que se desarrollan parten de la idea de su integración en un receptor totalmente digital. Son técnicas de procesado digital de señales. Se aborda el problema de la sincronización de portadora dando como solución diversos algoritmos que operan basándose en diferentes principios y obtienen diferentes características. Se destacan las ventajas e inconvenientes de cada uno de ellos y se presentan resultados de su funcionamiento. Respecto a la sincronización de bit se aborda el caso del empleo de interpoladores basados en la interpolación matemática para tal fin. Se trata de una técnica de cambio de velocidad de muestreo de forma dinámica para que las muestras de salida estén situadas en los instantes de muestreo óptimos. El interpolador lleva asociados un detector de error de sincronismo de bit y un sistema de control del interpolador. En el caso del detector de error se ha partido de la premisa de obtener un detector sencillo, de baja carga computacional y eficiente. El algoritmo se ha basado en el cruce por cero de la señal en las alternancias