NC-G-SIM: A Parameterized Generic Simulator for 2D-Mesh, 3D-Mesh

As chip density keeps doubling during each course of generation, the use of NoC has become an integral part of modern microprocessors and a very prevalent architectural feature of all types of SoCs. To meet the ever expanding communication challenges, diverse and novel NoC solutions are being developed which rely on accurate modeling and simulations to evaluate the impact and analyze their performances. Consequently, this aggravates the need to rely on simulation tools to probe and optimize these NoC architectures. In this work, we present NC-G-SIM (Network on Chip-Generic-SIMulator), a highly flexible, modular, cycle-accurate, configurable simulator for NoCs. To make NC-G-SIM suitable for advanced NoC exploration, it is made highly generic that supports extensive range of cores in any kind of topology whether 2D, 3D or irregular. Simulation results have been evaluated in terms of latencies, throughput and the amount of energy consumed during the simulation period at different levels

An Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks

On-chip communication, modular, scalable packet-switched micro-network of interconnects, generally known as Network-on-Chip (NoC) architecture can be designed as regular or application-specific (irregular) network topologies. Application specific custom network topologies are advantageous in terms of optimized design according to given performance metrics and regular network topologies are advantageous in terms of its modularity, lower design time and efforts required and thus are suitable for mass production. So to offer the advantages of both the topologies this paper proposes a methodology to augment the regular topology according to the application characteristics. The experimental results demonstrate that the proposed methodology can reduce dynamic communication energy consumption by on average of 32.79% and reduction in average per flit latency by on average of 16.22% over regular 2D NoC architecture

Energy Efficient Mapping in 3D Mesh Communication Architecture for NoC

By the end of this decade we will be entering into the era of thousand cores SoCs. 3D integration technologies have opened the door of new opportunities for NoC architecture design in SoCs providing higher efficiency compared to 2D integration by appropriately adjusting the increased path lengths of 2D NoC. The application to core mapping on NoC architecture can significantly affect the amount of system's dynamic communication energy consumption. The considerable amount of energy savings can be achieved by appropriately optimizing the application to core mapping in NoC architecture. This paper presents a Branch-and-Bound heuristic for smart application to core mapping in 3D Mesh NoC architecture. Experimental results show that proposed heuristic saves about 42%-55% and 19%-28% of dynamic communication energy consumption in comparison to random mapping in 3D NoC communication architecture and the energy aware-mapping in 2D NoC architecture of same size, respectively

Analysis of Different Routing Algorithm for 2D-Torus Topology NoC Architecture under Load Variation

The recital of Network-on-Chip (NoC) depends on the underlying routing techniques. There are a lot of requirements that has to be met. Such performance metrics are minimum latency, least power and maximum throughput. This paper deals with XY route, PROM routing, FTXY routing and DyAD routing on 5x5 2D torus topology. The simulation is performed on nirgam NoC simulator version 2.1 for constant bit rate traffic condition. The simulation results reveals the dominance of XY, PROM, FTXY and DyAD algorithms depicting the minimum values of overall average latency per channel (in clock cycles per flit) as 0.409836 overall average latency per channel (in clock cycles per packet) as 6.2535, average throughput as 16.68, and total network power as 35.6768 mw, achieved for FTXY routing algorithm

An analysis and Simulation Tool of Real-Time Communications in On-Chip Networks: A Comparative Study

International audienceThis paper presents Real-Time Network-on-chip-based architecture Analysis and Simulation tool (ReTiNAS), with a special focus on real-time communications. It allows fast and precise exploration of real-time design choices onto NoC architectures. ReTiNAS is an event-based simulator written in Python. It implements different real-time communication protocols and tracks the communications within the NoC at cycle level. Its modularity allows activating and deactivating different NoC components and easily extending the implemented protocols for more customized simulations and analysis. Further, we use ReTiNAS to perform a comparative study of analysis and simulation for different communication protocols using a wide set of synthetic experiments