2 research outputs found
N-term Karatsuba Algorithm and its Application to Multiplier designs for Special Trinomials
In this paper, we propose a new type of non-recursive Mastrovito multiplier for using a -term Karatsuba algorithm (KA), where is defined by an irreducible trinomial, . We show that such a type of trinomial combined with the -term KA can fully exploit the spatial correlation of entries in related Mastrovito product matrices and lead to a low complexity architecture. The optimal parameter is further studied.
As the main contribution of this study, the lower bound of the space complexity of our proposal is about . Meanwhile, the time complexity matches the best Karatsuba multiplier known to date. To the best of our knowledge, it is the first time that Karatsuba-based multiplier has reached such a space complexity bound while maintaining relatively low time delay
Low-delay FPGA-based implementation of finite field multipliers
Arithmetic operations over binary extension fields GF(2^m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2^m) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2^m) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2^m) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area x Time complexities when compared with similar multipliers found in the literature