3,301 research outputs found

    Cognitive Radio-Modulation and Demodulation

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    The reconfigurability in Cognitive Radio (CR) facilitates to dynamically change its parameters for the efficient spectrum utilization. The motivation behind the study of cognitive radio is that the number of different radio signals can be handled without using extra circuitry, i.e., reusing identical hardware with the change in the software will reduce time to market, development cost, and upgrade infrastructure. Software Defined Radio (SDR) is an enabling technology for Cognitive Radio (CR); therefore, it emphasizes on SDR unique features, characteristics, and basics concepts that are required to understand operation of SDR. SDR allows service providers to upgrade infrastructure without unreasonable cost. Modulation techniques play a vital role in any communication systems such as cable modems, DSL modems, CDMA, 4G, Wi-Fi, and WIMAX; thus, it emphasizes on implementation of modulation techniques using SDR Generic hardware, which is operated by Open Source software called GNU Radio. Implementation of various analog and digital modulation techniques using the GNU Radio provides a way for developing advanced wireless communication system. GNU Radio software is a highly flexible signal processing platform, which makes it easy and reduces time to implement different modulation techniques with appropriate script

    Modified DA based FIR Filter in Multirate DSP systems on FPGA

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    Multirate systems are popular in DSP.Systems which employ multiple sampling rates in the processing of digital signals are called Multirate DSP systems, which are used in audio, video processing and communication systems. Multirate DSP systems that employ different chips for different frequency signal results in more area and power utilization. The setback can be avoided by implementing Multirate system, based on Distributed Arithmetic FIR filter. Using such systems, we can achieve computation efficiency and improve the system performance. Modified DA based FIR Filter using Multirate systems includes decimation, interpolation process implemented on FPGA with 53% less LUT utilization compared to existing Multirate system

    Partial Binary Tree Network (Pbtn): A New Dynamic Element Matching (Dem) Approach To Current Steering Digital Analog Converter (Dac)

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    DACs are essential operations in many digital system which required high performance data converters. With shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures highly relying on matched components to perform data converters. However, components matched are nearly impossible to fabricate, there are always mismatch errors which caused the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. With this technique, the time averages of the equivalent components at each of the component positions are equal or nearly equal to reduce the effects of component differences in electronic circuits. The drawback of existing works is DAC would suffer from excessive digital hardware complexity. A complicated encoding is usually necessary for conventional DEM encoders which will lead to a lot of switch transitions at the same time and it will bring glitches to the output signal. In this research, a new DEM algorithm is proposed on Current-Steering DACs with Partial Binary Tree Network (PBTN) algorithm to overcome glitches transitions with low complexity. The analysis related to the performance of DAC such as glitch impulse areas, Integral Nonlinearity (INL), Differential Nonlinearity (DNL) and power consumption are shown to be equivalent and have at least 56% hardware efficient implementations compared to exiting DEM algorithm. Simulation results for 3-bit and 4-bit PBTN compared with 3-bit and 4-bit conventional Binary Tree Network (BTN) show that both algorithms are equivalent in performance with DNL and INL errors of +/- 0.2 LSB and the proposed algorithm has even lower power consumption due to small amount of transmission gates used. Simulation results for 8-bit PBTN with 1MSB randomization achieved INL of 1.5385 LSB and DNL 0.2605 LSB with power consumption of 22.2 mW. Besides that, PBTN algorithm provides the flexibility to improve the DAC performance by increasing numbers of randomization implementation on MSB

    Low Latency Audio Processing

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    PhDLatency in the live audio processing chain has become a concern for audio engineers and system designers because significant delays can be perceived and may affect synchronisation of signals, limit interactivity, degrade sound quality and cause acoustic feedback. In recent years, latency problems have become more severe since audio processing has become digitised, high-resolution ADCs and DACs are used, complex processing is performed, and data communication networks are used for audio signal transmission in conjunction with other traffic types. In many live audio applications, latency thresholds are bounded by human perceptions. The applications such as music ensembles and live monitoring require low delay and predictable latency. Current digital audio systems either have difficulties to achieve or have to trade-off latency with other important audio processing functionalities. This thesis investigated the fundamental causes of the latency in a modern digital audio processing system: group delay, buffering delay, and physical propagation delay and their associated system components. By studying the time-critical path of a general audio system, we focus on three main functional blocks that have the significant impact on overall latency; the high-resolution digital filters in sigma-delta based ADC/DAC, the operating system to process low latency audio streams, and the audio networking to transmit audio with flexibility and convergence. In this work, we formed new theory and methods to reduce latency and accurately predict latency for group delay. We proposed new scheduling algorithms for the operating system that is suitable for low latency audio processing. We designed a new system architecture and new protocols to produce deterministic networking components that can contribute the overall timing assurance and predictability of live audio processing. The results are validated by simulations and experimental tests. Also, this bottom-up approach is aligned with the methodology that could solve the timing problem of general cyber-physical systems that require the integration of communication, software and human interactions

    ADSL analogno sučelje

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    In this paper the Asymmetric Digital Subscriber Line (ADSL) analog front end (AFE) designs are described and compared. AFE is the part of ADSL modems most responsible for quality signal transmission over phone wires. It can be divided into the transmitting path (TX) circuitry, the receiving path (RX) circuitry and the hybrid network and transformer. The operations and realizations of each functional block are presented. There are the D/A converter, the filter and the line driver in the TX path and the voltage gain amplifier, the filter and the A/D converter in the RX path. The hybrid network and transformer process signals in both directions. Different fabrication technologies are used for the practical realizations of the AFE chip. The directions of the further developing are notified.U radu su opisane i uspoređene izvedbe ADSL analognog sučelja. Analogno sučelje kao dio ADSL modema najodgovornije je za kvalitetan prijenos signala preko telefonskih žica. Može se podijeliti u sklopove predajnog puta, prijamnog puta i hibridnu mrežu s transformatorom. Prikazan je rad i izvedbe svakog funkcijskog bloka. To su D/A pretvornik, filtar i izlazno pojačalo u predajnom putu te ulazno pojačalo, filtar i A/D pretvornik u prijamnom putu. Hibridna mreža i transformator prosljeđuju signale u oba smjera. Za praktičnu izvedbu AFE čipa koriste se razne tehnologije. Naznačene su smjernice daljnjeg razvoja

    Advanced Television and Signal Processing Program

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    Contains an introduction and reports on fifteen research projects.Advanced Television Research ProgramAdams-Russell Electronics, Inc.National Science Foundation Fellowship Grant MIP 87-14969National Science Foundation FellowshipU.S. Navy - Office of Naval Research Grant N00014-89-J-1489U.S. Air Force - Electronic Systems Division Contract F1 9628-89-K-004
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