Monolithic integration of tunnel diode based inverters on exact (001) Si substrates

Monolithic integration of tunnel diode-based inverters on exact (001) Si substrates for the future high-speed, low-power, and compact digital circuits is demonstrated. A two-state inverter was fabricated using a forward biased fin-array tunnel diode as drive and a reverse-biased counterpart as load. On-chip operation and reduced fabrication complexity were achieved by exploiting the resistive characteristic of the reverse-biased tunnel diodes and the pre-defined patterns on the Si substrat

Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

Challenges and Opportunities in Implementing Negative Differential Resistance Mode Reconfigurable Field Effect Transistors

Desirably, the world relies on the devices being compact, as they could drive to the increased functionality of integrated circuits at the provided footstep, that is becoming more reliable. To reduce the scalability over the devices, approach has been outlined utilizing the NDR mode reconfigurable functionality over the transistors. Being an individual device efficient in exhibiting different task with the different configurations in the same physical circuitry. On the view of reconfigurable transistors, possibly authorize the reconfiguration from a p-type to n-type channel transistor has been expelled as an emerging application such as static memory cells, fast switching logic circuits as well as energy efficient computational multi valued logic. This article emphasizes NDR mode RFET along with its classification, followed by enhancing the RFET technology concepts and RFETs future potential has been discussed briefing with the growing applications like hardware security as well as neuro-inspired computing.Comment: 28 pages, 9 figure

Atomically Thin Resonant Tunnel Diodes built from Synthetic van der Waals Heterostructures

Vertical integration of two-dimensional van der Waals materials is predicted to lead to novel electronic and optical properties not found in the constituent layers. Here, we present the direct synthesis of two unique, atomically thin, multi-junction heterostructures by combining graphene with the monolayer transition-metal dichalocogenides: MoS2, MoSe2, and WSe2.The realization of MoS2-WSe2-Graphene and WSe2-MoSe2-Graphene heterostructures leads toresonant tunneling in an atomically thin stack with spectrally narrow room temperature negative differential resistance characteristics

Development of tunnel diode devices and models for circuit design and characterization

Historically, the microelectronics industry has scaled down CMOS transistor dimensions in order to increase operating speeds, decrease cost per transistor, and free up on-chip real estate for additional chip functions. There are numerous challenges involved with scaling transistors down to the near term 32 nm node, and beyond. These challenges include short gate lengths, very thin gate oxides, short channel effects, quantum effects, band-to-band tunneling from source to drain, Gate Induced Drain Leakage, Fowler Nordheim tunneling, and increasing dopant concentrations. Field effect transistor circuits augmented with tunnel diodes lead to decreased circuit footprints, decreased device count, improved operating speeds, and lower power consumption without the need to solve current CMOS scaling challenges. Recently, N on P Si/SiGe resonant interband tunnel diodes (RITD) have been monolithically integrated with CMOS transistors. To further improve the benefits of RITD augmented circuits, P-on-N RITDS and all-Si RITDs were developed. Reported maximum peak to valley current ratios (PVCR), a key quantitative parameter of TDs, of 1.32 and 3.02 were measured, respectively. Since integrated circuits operate at elevated temperatures, the I-V characteristics of various TDs were measured at temperatures ranging from room temperature up to 200oC. Three figures of merit were extracted; (i) peak current density (JP), (ii) valley current density (JV), and (iii) PVCR. Normalizing over their respective values at room temperature allowed for direct comparison between the various TD structures. This method allowed the author to determine that all devices show a similar JP response. However, the Si/SiGe RITD structure was overall least sensitive to temperature variations. Furthermore, to design and optimize TD augmented circuits, a SPICE compatible model was developed. Past models have discontinuities, kinks in their slopes, difficult parameters to extract, unknown parameters, no closed form solutions, and/or poor fits to measured data. For this work a modified version of the S. M. Sze model with a superior match to experimental data, for Si based Esaki tunnel diodes (ETD) was developed. Using the developed model, several circuits were simulated, which were broken up into two groups. The first group of circuits is comprised of one TD and one of the following; (i) resistor, (ii) NMOS transistor, or (iii) TD. Finally, the behaviors learned from the simple circuits were used to simulate several TD augmented circuits such as (i) ADC comparator, (ii) TSRAM, (iii) and four basic logic gates

Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications

Department of Electrical EngineeringMotivation of this work is to provide feasible, scalable, and designable multi-valued logic (MVL) device platform for physical synthesis of MVL circuits. Especially, ternary device and its general logic functions are focused, owing to most efficiently reduced circuit complexity per radix (R) increase. By designing the OFF-state constant current, not only the standby power (PS) issue of additional intermediate state is overcome, but also continuous supply voltage (VDD) scaling and dynamic power (PD) scaling are possible owing to single-step I-V characteristics. By applying a novel ternary device concept to CMOS technology with OFF-state current mechanism of band-to-band tunneling (BTBT) currents (IBTBT) and subthreshold diffusion current (Isub), the logic changes from binary to ternary are confirmed using mixed-mode device simulation. I experimentally demonstrate ternary CMOS (T-CMOS) and verified its low-power standard ternary inverter (STI) operation by designing channel profiles in conventional binary CMOS. The realized complementary ternary n/pMOS (T-n/pMOS) have fully gate bias (VG)-independent and symmetrical IBTBT of ~10 pA/???m based on proven ion-implantation process, which produces stable and designable intermediate state (VOM) at exactly VDD/2. To present T-CMOS design frameworks in terms of static noise margin (SNM) enhancement and ultra-low power operation, I develop the compact model of T-CMOS and verify the physical model parameters with experimental data. Through the feasible design of Isub with abrupt channel profile based on low thermal budget process, STI has a SNM of 283 mV (80 % of ideal SNM) at VDD= 1V operation and intermediate state stability of ??VOM < ?? 0.1V, even considering the random-dopant fluctuation (RDF) of 32 nm and 22 nm technology. Continuous VDD scaling below 0.5V (SNM= 40% at VDD = 0.3V) enables STI operation with ultra-low PD and PS based on exponentially reduced IBTBT currents. As MVL and memory (MVM) applications, minimum(MIN)/maximum(MAX) gates, analog-to-digital converter (ADC) circuit, and 5-state latch are studied with T-CMOS compact model. Especially ADC circuits revolutionary decreases number of device and circuit interconnection with 9.6% area of binary system.ope

GaAs-InGaAs-GaAs fin-array tunnel diodes on (001) Si substrates with room-temperature peak-to-valley current ratio of 5.4

In this letter, we report the selective area growth of GaAs, In0.2Ga0.8As, and GaAs/In0.2Ga0.8As/GaAs quantum-well fins of 65-nm width on exactly orientated (001) Si substrates. By exploiting high aspect ratio trenches formed by patterned SiO2 on Si and a V-grooved Si (111) surface in the aspect ratio trapping process, we are able to achieve good material quality and structural properties, as evidenced by x-ray diffraction, scanning electron microscopy, and transmission electron microscopy. The fabricated GaAs-In0.2Ga0.8As-GaAs fin-array tunnel diodes exhibit a maximum room-temperature peak-to-valley current ratio of 5.4, and negative differential resistance characteristics up to 200 °C

Hybrid MOS and Single-Electron Transistor Architectures towards Arithmetic Applications

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Single-Electron Transistor (SET) hybrid architectures, which combine the merits of both MOSFET and SET, promise to be a practical implementation for nanometer-scale circuit design. In this thesis, we design arithmetic circuits, including adders and multipliers, using SET/MOS hybrid architectures with the goal of reducing circuit area and power dissipation and improving circuit reliability. Thanks to the Coulomb blockade oscillation characteristic of SET, the design of SET/MOS hybrid adders becomes very simple, and requires only a few transistors by using the proposed schemes of multiple-valued logic (MVL), phase modulation, and frequency modulation. The phase and frequency modulation schemes are also utilized for the design of multipliers. Two types of SET/MOS hybrid multipliers are presented in this thesis. One is the binary tree multiplier which adopts conventional tree structures with multi-input counters (or compressors) implemented with the phase modulation scheme. Compared to conventional CMOS tree multipliers, the area and power dissipation of the proposed multiplier are reduced by half. The other is the frequency modulated multiplier following a novel design methodology where the information is processed in the frequency domain. In this context, we explore the implicit frequency properties of SET, including both frequency gain and frequency mixing. The major merits of this type of multiplier include: a) simplicity of circuit structure, and b) high immunity against background charges within SET islands. Background charges are mainly induced by defects or impurities located within the oxide barriers, and cannot be entirely removed by today\u27s technology. Since these random charges deteriorate the circuit reliability, we investigate different circuit solutions, such as feedback structure and frequency modulation, in order to counteract this problem. The feedback represents an error detection and correction mechanism which offsets the background charge effect by applying an appropriate voltage through an additional gate of SET. The frequency modulation, on the other hand, exploits the fact that background charges only shift the phase of Coulomb blockade oscillation without changing its amplitude and periodicity. Therefore, SET/MOS hybrid adders and multipliers using the frequency modulation scheme exhibit the high immunity against these undesired charges

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency