Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

Tristate memory cells using double-peaked fin-array III-V tunnel diodes monolithically grown on (001) silicon substrates

We demonstrate functional tristate memory cells using multipeaked GaAs/InGaAs fin-array tunnel diodes grown on exact (001) Si substrates. On-chip connection of single-peaked tunnel diode arrays produces I–V characteristics with multiple negative-differential resistance regions. We designed and fabricated two types of tristate memory cells. In one design, a double-peaked tunnel diode was used as the drive, and a reverse-biased single-peaked tunnel diode was used as the load. In the other design, the tristate memory cell was realized by the series connection of two forward-biased single-peaked tunnel diode

Monolithic integration of tunnel diode based inverters on exact (001) Si substrates

Monolithic integration of tunnel diode-based inverters on exact (001) Si substrates for the future high-speed, low-power, and compact digital circuits is demonstrated. A two-state inverter was fabricated using a forward biased fin-array tunnel diode as drive and a reverse-biased counterpart as load. On-chip operation and reduced fabrication complexity were achieved by exploiting the resistive characteristic of the reverse-biased tunnel diodes and the pre-defined patterns on the Si substrat

Fin-array tunneling trigger with tunable hysteresis on (001) silicon substrate

We report the fabrication and characterization of a GaAs fin-array tunneling trigger monolithically integrated on an exact (001) silicon substrate. A Schmitt-trigger-like behavior was observed under double sweep condition by connecting the tunnel diode with an on-chip load resistor. The tunneling trigger circuit was studied using load line analysis. Critical parameters of the circuit were extracted. We found that the circuit hysteresis can be tuned by tailoring of the diode dimensions and load resistor value

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics, due to its exotic properties. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, a multi-state memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called Graphene Nanoribbon Tunneling Random Access Memory (GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations. A comprehensive design for quaternary GNTRAM is presented as a baseline, implemented with a heterogeneous integration between graphene and CMOS. Sources of leakage and approaches to mitigate them are investigated. This design is extensively benchmarked against 16nm CMOS SRAMs and 3T DRAM. The proposed quaternary cell shows up to 2.27x density benefit vs. 16nm CMOS SRAMs and 1.8x vs. 3T DRAM. It has comparable read performance and is power-efficient, up to 1.32x during active period and 818x during stand-by against high performance SRAMs. Multi-state GNTRAM has the potential to realize high-density low-power nanoscale embedded memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future

The integration of Si-based resonant interband

eports the first demonstration of the integration of CMOS and Si/SiGe resonant interband tunnel diode (RITD). In Si-based material, recent breakthrough in Si/SiGe RITD grown using molecular beam epitaxy (MBE) made the integration with CMOS possible. The resultant devices enabled the realization of RITD CMOS circuitry, and a NMOS-RITD MOBILE latch was demonstrated in Si, all enabling digital and ternary circuit design for density storag

GaAs-InGaAs-GaAs fin-array tunnel diodes on (001) Si substrates with room-temperature peak-to-valley current ratio of 5.4

In this letter, we report the selective area growth of GaAs, In0.2Ga0.8As, and GaAs/In0.2Ga0.8As/GaAs quantum-well fins of 65-nm width on exactly orientated (001) Si substrates. By exploiting high aspect ratio trenches formed by patterned SiO2 on Si and a V-grooved Si (111) surface in the aspect ratio trapping process, we are able to achieve good material quality and structural properties, as evidenced by x-ray diffraction, scanning electron microscopy, and transmission electron microscopy. The fabricated GaAs-In0.2Ga0.8As-GaAs fin-array tunnel diodes exhibit a maximum room-temperature peak-to-valley current ratio of 5.4, and negative differential resistance characteristics up to 200 °C

Tunnel Junction-Embedded Field-Effect Transistor for Negative Differential Resistance and Its Multi-Valued Logic and Memory Applications

Device PhysicsI propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn tunnel diode with transistor. The embedded transistors suppress the valley current with transistor off-leakage current level. With various configurations of pn diode and transistor, single or multiple NDR characteristics obtained and each operation principle is explained clearly. Each composed device is analyzed in detail and NDR characteristics are examined device design parameters. In the single NDR case, operation voltage is below 0.5V, which is good at power density. In the multiple NDR case, band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and second peak and valley are generated from the suppression of diode current by off-state transistor. For the digital applications, introduced tri-state voltage transfer circuit makes NDR device take single input operation. Moreover, by using complementary multiple NDR devices, 5-state memory is demonstrated only with four transistors.ope