21,435 research outputs found

    Strategies for synthesis of yardsticks and abaci for nanometre distance measurements by pulsed EPR

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    Silvia Valera is grateful for support by EPSRC and Bela E. Bode acknowledges support by EastCHEM.Pulsed electron paramagnetic resonance (EPR) techniques have been found to be an efficient tool for elucidation of structure in complex biological systems as they give access to distances in the nanometre range. These measurements can provide additional structural information such as relative orientations, structural flexibility or aggregation states. A wide variety of model systems for calibration and optimisation of pulsed experiments has been synthesised. Their design is based on mimicking biological systems or materials in specific properties such as the distances themselves and the distance distributions. Here, we review selected approaches to the synthesis of chemical systems bearing two or more spin centres, such as nitroxide or trityl radicals, metal ions or combinations thereof and sketch their application in pulsed EPR distance measurements.Publisher PDFPeer reviewe

    On orbit validation of solar sailing control laws with thin-film spacecraft

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    Many innovative approaches to solar sail mission and trajectory design have been proposed over the years, but very few ever have the opportunity to be validated on orbit with real spacecraft. Thin- Film Spacecraft/Lander/Rovers (TF-SL Rs) are a new class of very low cost, low mass space vehicle which are ideal for inexpensively and quickly testing in flight new approaches to solar sailing. This paper describes using TF- SLR based micro solar sails to implement a generic solar sail test bed on orbit. TF -SLRs are high area- to-mass ratio (A/m) spacecraft developed for very low cost consumer and scientific deep space missions. Typically based on a 5 μm or thinner metalised substrate, they include an integrated avionics and payload system -on-chip (SoC) die bonded to the substrate with passive components and solar cells printed or deposited by Metal Organic Chemical Vapour Deposition (MOCVD). The avionics include UHF/S- band transceivers, processors, storage, sensors and attitude control provided by integrated magnetorquers and reflectivity control devices. Resulting spacecraft have a typical thickness of less than 50 μm, are 80 mm in diameter, and have a mass of less than 100 mg resulting in sail loads of less than 20 g/m 2 . TF -SLRs are currently designed for direct dispensing in swarms from free flying 0.5U Interplanetary CubeSats or dispensers attached to launch vehicles. Larger 160 mm, 320 mm and 640 mm diameter TF -SLRs utilizing a CubeSat compatible TWIST deployment mechanism that maintains the high A/m ratio are also under development. We are developing a mission to demonstrate the utility of these devices as a test bed for experimenting with a variety of mission designs and control laws. Batches of up to one hundred TF- SLRs will be released on earth escape trajectories, with each batch executing a heterogeneous or homogenous mixture of control laws and experiments. Up to four releases at different points in orbit are currently envisaged with experiments currently being studied in MATLAB and GMA T including managing the rate of separation of individual spacecraft, station keeping and single deployment/substantially divergent trajectory development. It is also hoped to be able to demonstrate uploading new experiment designs while in orbit and to make this capability available to researchers around the world. A suitable earth escape mission is currently being sought and it is hoped the test bed could be on orbit in 2017/18

    Fast, Accurate and Detailed NoC Simulations

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    Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy

    Using an FPGA for Fast Bit Accurate SoC Simulation

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    In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy

    A case study for NoC based homogeneous MPSoC architectures

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    The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo
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