Exact and heuristic allocation of multi-kernel applications to multi-FPGA platforms

FPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. However, single FPGA designs may not achieve sufficient task parallelism. In this work, we optimize the mapping of high-performance multi-kernel applications, like Convolutional Neural Networks, to multi-FPGA platforms. First, we formulate the system level optimization problem, choosing within a huge design space the parallelism and number of compute units for each kernel in the pipeline. Then we solve it using a combination of Geometric Programming, producing the optimum performance solution given resource and DRAM bandwidth constraints, and a heuristic allocator of the compute units on the FPGA cluster.Peer ReviewedPostprint (author's final draft

Live Demonstration: Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock- Correction for Scalable Neuromorphic Systems

In this live demonstration we exploit the use of a serial link for fast asynchronous communication in massively parallel processing platforms connected to a DVS for realtime implementation of bio-inspired vision processing on spiking neural networks

The MANGO Process for Designing and Programming Multi-Accelerator Multi-FPGA Systems

[EN] This paper describes the approach followed in the European FETHPC MANGO project to design and program systems made of multiple FPGAs interconnected. The MANGO approach relies on the instantiation and management of multiple generic and custom-made accelerators which can be programmed to communicate each other via shared memory and through synchronization registers. The paper introduces the low level architecture including the multi-FPGA interconnect deployed, the communication protocol and the architectural template-based approach to simplify the design process.This work is supported by the European Commission through MANGO project, under the Horizon 2020 FET-HPC program, grant number 671668.Tornero-Gavilá, R.; Flich Cardo, J.; Martínez Martínez, JM.; Picornell-Sanjuan, T.; Scotti, V. (2018). The MANGO Process for Designing and Programming Multi-Accelerator Multi-FPGA Systems. En Fourth International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC'18). ACM. http://hdl.handle.net/10251/114284

Two IP Protection Schemes for Multi-FPGA Systems

International audienceThis paper proposes two novel protection schemes for multi-FPGA systems providing high security of IP designs licensed by IP vendors to system integrators and installed remotely in a hostile environment. In the first scheme, these useful properties are achieved by storing two different configuration keys inside an FPGA, while in the second scheme, they are obtained using a hardware white-box cipher for creating a trusted environment. Thanks to the proposed principles, FPGA configurations coming from different IP owners cannot be cloned or reverse-engineered by any involved party, including system integrator and other IP owners. The proposed schemes can be directly implemented in recent FPGAs such as Xilinx Spartan 6 and Virtex 6