More Accurate Analysis of Sum-Product Decoding of LDPC codes Using a Gaussian Approximation

This letter presents a more accurate mathematical analysis, with respect to the one performed in Chung et al.\u2019s 2001 paper, of belief-propagation decoding for Low-Density Parity- Check (LDPC) codes on memoryless Binary Input - Additive White Gaussian Noise (BI-AWGN) channels, when considering a Gaussian Approximation (GA) for message densities under density evolution. The recurrent sequence, defined in Chung et al.\u2019s 2001 paper, describing the message passing between variable and check nodes, follows from the GA approach and involves the function \u3c6(x), therein defined, and its inverse. The analysis of this function is here resumed and studied in depth, to obtain tighter upper and lower bounds on it. Moreover, unlike the upper bound given in the above cited paper, the tighter upper bound on \u3c6(x) is invertible. This allows a more accurate evaluation of the asymptotical performance of sum-product decoding of LDPC codes when a GA is assumed

Limiting Performance of Millimeter-Wave Communications in the Presence of a 3D Random Waypoint Mobility Model

This paper proposes a mathematical framework for evaluating the limiting capacity of a millimeter-wave (mmWave) communication involving a mobile user (MU) and a cellular base station. The investigation is realized considering a threedimensional (3D) space in which the random waypoint mobility model is used to probabilistically identify the location of the MUs. Besides, the analysis is developed accounting for path-loss attenuation, directional antenna gains, shadowing, and modulation scheme. Closed-form formulas for the received signal power, the Shannon capacity, and the bit error rate (BER) are obtained for both line-of-sight (LoS) and non-LoS scenarios in the presence of a noise-limited operating regime. The conceived theoretical model is firstly checked by Monte Carlo validations, and then employed to explore the influence of the antenna gain and of the cell radius on the capacity and on the BER of a fifth-generation (5G) link in a 3D environment, taking into account both the 28 and 73 GHz mmWave bands

Performance Study of a Class of Irregular Near Capacity Achieving LDPC Codes

This paper investigates the performance of a class of irregular low-density parity-check (LDPC) codes through a recently published low complexity upper bound on their beliefpropagation decoding thresholds. Moreover, their performance analysis is carried out through a recently published algorithmic method, presented in Babich et al. 2017 paper. In particular, the class considered is characterized by variable node degree distributions λ(x) of minimum degree i1 > 2: being, in this case, λ0(0) = λ2 = 0, this is useful to design LDPC codes presenting a linear minimum distance growth with the block length with probability 1, as shown in Di et al.'s 2006 paper. These codes unfortunately cannot reach capacity under iterative decoding, since the achievement of capacity requires λ2 ≠ 0. However, in this latter case, the block error probability might converge to a constant, as shown in the aforementioned paper

Performance Study of a Class of Irregular Near Capacity Achieving LDPC Codes

This paper investigates the performance of a class of irregular low-density parity-check (LDPC) codes through a recently published low complexity upper bound on their belief propagation decoding thresholds. Moreover, their performance analysis is carried out through a recently published algorithmic method, presented in Babich et al. 2017 paper. In particular, the class considered is characterized by variable node degree distributions (lambda(x)) of minimum degree (i_1 gt 2): being, in this case, (lambda^{\u27} (0)=lambda_2=0), this is useful to design LDPC codes presenting a linear minimum distance growth with the block length with probability 1, as shown in Di et al.’s 2006 paper. These codes unfortunately cannot reach capacity under iterative decoding, since the achievement of capacity requires (lambda_2 neq 0). However, in this latter case, the block error probability might converge to a constant, as shown in the aforementioned paper

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investigated by Cullinan et al. in a recent paper (published in 2012) where these three devices capabilities were compared to determine which device would be best suited towards which specific task. In particular, it was shown that, for the application which is objective of our work (i.e., for a transmission channel simulation), the FPGA is 26.67 times faster than the GPU and 10.76 times faster than the CPU. Motivated by these results, in this paper we propose and present a direct hardware emulation. In particular, a Cyclone II FPGA architecture is implemented to simulate a burst error channel behaviour, in which errors are clustered together, and a burst erasure channel behaviour, in which the erasures are clustered together. The results presented in the paper are valid for any FPGA architecture that may be considered for this scope