Hierarchical gate-level verification of speed-independent circuits

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.Peer ReviewedPostprint (published version

Verification of timed circuits with failure-directed abstractions

Journal ArticleAbstract-This paper presents a method to address state explosion in timed-circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is analyzed. An algorithm is also shown to examine the abstract error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure-directed abstractions as applied to several large timed circuit designs

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology

Verification of timed circuits with failure directed abstractions

Journal ArticleThis paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is analyzed. An algorithm is also shown to examine the abstract error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure directed abstractions as applied to two large timed circuit designs

Synthesis of timed circuits based on decomposition

Journal ArticleAbstract-This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals, which must be reintroduced into the STG to obtain complete state coding. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full-state-space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool Nii-Utah Timed Asynchronous circuit Synthesis system (nutas), and its first version is available at http://research.nii.ac.jp/~yoneda

Synthesis of speed independent circuits based on decomposition

Journal ArticleThis paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the STG to include only transitions on the output of interest and its trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas (Nii-Utah Timed Asynchronous circuit Synthesis system), and its very first version is available at http://research.nii.ac.jp/~yoneda. Key Words: Decomposition, synthesis, STGs, abstraction, speed-independent circuits

Petri net modeling and analysis of an FMS cell

Petri nets have evolved into a powerful tool for the modeling, analysis and design of asynchronous, concurrent systems. This thesis presents the modeling and analysis of a flexible manufacturing system (FMS) cell using Petri nets. In order to improve the productivity of such systems, the building of mathematical models is a crucial step. In this thesis, the theory and application of Petri nets are presented with emphasis on their application to the modeling and analysis of practical automated manufacturing systems. The theory of Petri nets includes their basic notation and properties. In order to illustrate how a Petri net with desirable properties can be modeled, this thesis describes the detailed modeling process for an FMS cell. During the process, top-down refinement, system decomposition, and modular composition ideas are used to achieve the hierarchy and preservation of important system properties. These properties include liveness, boundedness, and reversibility. This thesis also presents two illustrations showing the method adopted to model any manufacturing systems using ordinary Petri nets. The first example deals with a typical resource sharing problem and the second the modeling of Fanuc Machining Center at New Jersey Institute of Technology. Furthermore, this thesis presents the analysis of a timed Petri net for cycle time, system throughput and equipment utilization. The timed (deterministic) Petri net is first converted into an equivalent timed marked graph. Then the standard procedure to find the cycle time for marked graphs is applied. Secondly, stochastic Petri net is analyzed using SPNP software package for obtaining the system throughput and equipment utilization. This thesis is of significance in the sense that it provides industrial engineers and academic researchers with a comprehensive real-life example of applying Petri net theory to modeling and analysis of FMS cells. This will help them develop their own applications

Automatic abstraction for synthesis and verification of deterministic timed systems

Journal ArticleThis paper presents a new approach for synthesis and verification of asynchronous circuits by using abstraction. It attacks the state explosion problem by avoiding the generation of a flat state space for the whole design. Instead, it breaks the design into sub-blocks and conducts synthesis and verification on each of them. Using this approach, the speed of synthesis and verification improves dramatically. This paper introduces how abstraction is applied to times Petri-nets to speed up synthesis and verification

A compositional minimization approach for large asynchronous design verification

pre-printThis paper presents a compositional minimization approach with efficient state space reductions for verifying non-trivial asynchronous designs. These reductions can result in a reduced model that contains the exact same set of observably equivalent behavior in the original model, therefore no false counter-examples result from the verification of the reduced model. This approach allows designs that cannot be handled monolithically or with partial-order reduction to be verified without difficulty. The experimental results show significant scale-up of the compositional minimization approach using these reductions on a number of large asynchronous designs