Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction

This paper presents the design of a compact pro-tocol for fixed-latency, high-speed, reliable, serial transmissionbetween simple field-programmable gate arrays (FPGA) devices.Implementation of the project aims to delineate word boundaries,provide randomness to the electromagnetic interference (EMI)generated by the electrical transitions, allow for clock recov-ery and maintain direct current (DC) balance. An orthogonalconcatenated coding scheme is used for correcting transmissionerrors using modified Bose–Chaudhuri–Hocquenghem (BCH)code capable of correcting all single bit errors and most ofthe double-adjacent errors. As a result all burst errors of alength up to 31 bits, and some of the longer group errors,are corrected within 256 bits long packet. The efficiency of theproposed solution equals 46.48%, as 119 out of 256 bits arefully available to the user. The design has been implementedand tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kitwith a data rate of 28.2 Gbps. Sample latency analysis has alsobeen performed so that user could easily carry out calculationsfor different transmission speed. The main advancement of thework is the use of modified BCH(15, 11) code that leads to higherror correction capabilities for burst errors and user friendlypacket length