Modeling of glitch effects in FPGA based arithmetic circuits

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PowerBit - Power aware arithmetic bit-width optimization

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Fast word-level power models for synthesis of FPGA-based arithmetic

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Utilizing the Digital Fingerprint Method for Secure Key Generation

This research examines a new way to generate an uncloneable secure key by taking advantage of the delay characteristics of individual transistors. The user profiles the circuit to deduce the glitch count of each output line for each number of selectable buffers added to the circuit. The user can then use this information to generate a specific glitch count on each output line, which is passed to an encryption algorithm as its key. The results detail tests of two configurations for adding a selectable amount of buffers into each glitch circuit in order to induce additional delay. One configuration adds up to seven buffers that is equivalent to the binary digits used on the three SELECT lines of a multiplexer. The second, referred to as the cascaded design, has eight different quantities of selectable buffers, but they all connect to one multiplexer. Each successive line connects to the previous line and adds a certain number of buffers. The linear selection implementation produces almost 15% more usable output lines over the cascaded design, where a usable line is defined as one that has at least one ‘1’ and one ‘0’ glitch count in response to every buffer count. Tests were also performed to determine the optimal number of buffers added to each output using the linear buffer selection configuration. Using three input bits to the buffer unit produced 30.94% usable outputs. Four bits generated nearly 25% more usable outputs, while the use of six bits gave less than a 5% improvement over four bits. The average repeatability of the glitch count is 94.85% using this method. The overall distinguishability of the generated glitch counts for each output line is 10.46%

Research on performance enhancement for electromagnetic analysis and power analysis in cryptographic LSI

制度:新 ; 報告番号:甲3785号 ; 学位の種類:博士(工学) ; 授与年月日:2012/11/19 ; 早大学位記番号:新6161Waseda Universit

Critical Information Technology on FPGAs through Unique Device Specific Keys

Field Programmable Gate Arrays (FPGAs) are being used for military and other sensitive applications, the threat of an adversary attacking these devices is an ever present danger. While having the ability to be reconfigured is helpful for development, it also poses the risk of its hardware design being cloned. Static random access memory (SRAM) FPGA\u27s are the most common type of FPGA used in industry. Every time an SRAM-FPGA is powered up, its configuration must be downloaded. If an adversary is able to obtain that configuration, they can clone sensitive designs to other FPGAs. A technique that can be used to protect FPGAs from these types of attacks is known as Digital Fingerprinting (DF). DF takes advantage of the manufacturing variability that naturally occurs in the integrated circuit fabrication process. If another factor can be introduced making the FPGA\u27s operation dependent on more than the design specified within its configuration and response to external outputs, we can defend against cloning. This solution would allow for an FPGA\u27s operation to be dependent on how the downloaded configuration interacts with the hardware itself. This research uses DF technology to create unique device specific keys for use as encryption keys or control values for polymorphic circuits to protect information on FPGAs

Dynamic power consumption estimation and reduction for full search motion estimation hardware

Motion Estimation (ME) is the most computationally intensive and most power consuming part of video compression and video enhancement systems. ME is used in video compression standards such as MPEG4, H.264 and it is used in video enhancement algorithms such as frame rate conversion and de-interlacing. Since portable devices operate with battery, it is important to reduce power consumption so that the battery life can be increased. In addition, consuming excessive power degrades the performance of integrated circuits, increases packaging and cooling costs, reduces the reliability and may cause device failures. Therefore, estimating and reducing power consumption of motion estimation hardware is very important. In this thesis, we propose a novel dynamic power estimation technique for full search ME hardware. We estimated the power consumption of two full search ME hardware implementations on a Xilinx Virtex II FPGA using several existing high and low level dynamic power estimation techniques and our technique. Gate-level timing simulation based power estimation of full search ME hardware for an average frame using Xilinx XPower tool takes 6 - 18 hours in a state-of-the-art PC, whereas estimating the power consumption of the same ME hardware for the same frame takes a few seconds using our technique. The average and maximum difference between the power consumptions estimated by our technique and the power consumptions estimated by XPower tool for four different video sequences are %3 and %13 respectively. We also propose a novel dynamic power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex II FPGA using Xilinx XPower tool. Glitch reduction and clock gating together achieved an average of 21% dynamic power reduction. The proposed technique achieved an average of 23% dynamic power reduction with an average of 0.4dB PSNR loss. The proposed technique achieves better power reduction than pixel truncation technique with a similar PSNR loss. We also showed that our dynamic power estimation technique can be used for developing novel dynamic power reduction techniques. To do this, we used our technique to estimate the dynamic power consumption of the ME hardware when two different dynamic power reduction techniques are used. The results show that if a power reduction technique only changes the input data order of the ME hardware, the proposed dynamic power estimation technique can be used to quickly estimate the effectiveness of that technique. However, if the architecture of the ME hardware is modified, the accuracy of the power consumption estimations decrease. Therefore the proposed power estimation technique should be improved for this case