Dynamic gates with hysteresis and configurable noise tolerance

Journal ArticleDynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures

Relative timing

Journal ArticleRelative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases

An asynchronous instruction length decoder

Journal ArticleAbstract-This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process

An asynchronous instruction length decoder

Journal ArticleThis paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process

Relative timing

Journal ArticleAbstract-Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3x in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated

An asynchronous soft-output Viterbi algorithm decoder.

Chan Wing-kin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 69-72).Abstracts in English and Chinese.Abstract of this thesis entitled: --- p.ii摘要 --- p.ivAcknowledgements --- p.vTable of Contents --- p.viList of Figures --- p.viiiList of Tables --- p.xChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Communication Systems --- p.1Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2Chapter 1.3 --- Iterative Decoding --- p.3Chapter 1.4 --- Motivation --- p.3Chapter 1.5 --- Organization of the Thesis --- p.4Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5Chapter 2.1 --- Properties of Self-Timed Design --- p.5Chapter 2.2 --- Bundled-data Protocol --- p.7Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8Chapter 2.4 --- Completion-Detection and Delay Match --- p.9Chapter 2.5 --- Muller Pipeline --- p.11Chapter 2.6 --- Design of the Adder --- p.12Chapter 2.6.1 --- Basic Structure --- p.12Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12Chapter Chapter 3 --- SOVA Theory --- p.15Chapter 3.1 --- Convolutional Encoder --- p.15Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17Chapter 3.3.1 --- Viterbi Algorithm --- p.17Chapter 3.3.2 --- Soft Output Algorithm --- p.20Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24Chapter 4.1 --- Overview --- p.24Chapter 4.2 --- SOVA Decoder Architecture --- p.24Chapter 4.3 --- Branch Metric Unit --- p.26Chapter 4.3.1 --- Branch Metric Generation --- p.26Chapter 4.3.2 --- Implementation --- p.27Chapter 4.4 --- Add-Compare-Select Unit --- p.28Chapter 4.4.1 --- Basics --- p.28Chapter 4.4.2 --- Self-timed design --- p.28Chapter 4.4.3 --- Metric Normalization --- p.30Chapter 4.4.4 --- ACS Unit Implementation --- p.31Chapter 4.5 --- Traceback Unit --- p.33Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33Chapter 4.5.2 --- Two Step SOVA --- p.34Chapter 4.5.3 --- Past Designs --- p.36Chapter 4.5.4 --- New Traceback Architecture --- p.38Chapter 4.5.5 --- Traceback operation --- p.40Chapter 4.5.6 --- Traceback Implementation --- p.42Chapter 4.5.7 --- Control Signals --- p.48Chapter Chapter 5 --- Experimental Result and Discussion --- p.54Chapter 5.1 --- Chip Fabrication --- p.54Chapter 5.2 --- Measurements --- p.61Chapter Chapter 6 --- Conclusion --- p.67References --- p.69Appendix --- p.73Pin Assignment of the SOVA test chip --- p.7