Low Power FinFET based SRAM Cell Design

With the incessant developments occurring in VLSI circuits and systems arena and power dissipation becoming a major design constraint, the power component can be considerably reduced through efficient designing of the SRAM memory elements. Nowadays, multi-gate devices such as the FinFETs play a prominent role in reducing the power dissipation that what was found realizable by the conventional CMOS devices. Additionally, the FinFETs are found to be capable of overcoming some of the major drawbacks of the conventional CMOS devices, namely, the leakage current, the sub-threshold leakage, parasitic capacitance etc. This paper uses 32nm FinFET devices for the implementation of the 6T, 7T SRAM cell architectures and the resultant power is calculated for the read and write operations, to study the comparative benefits of the use of FinFETs in the memory cells than that of the CMOS counterpart circuits. Industry standard Cadence EDA tools have been employed for the simulations. The layout designs of 6T and 7T SRAM cells have been carried out using 180nm CMOS technology library for post layout simulations

Thermal and flicker noise improvement in short-channel CMOS detectors

Integrated circuit (IC) technology has emerged as a suitable platform for infrared (IR) detector development. This technology is however susceptible to on-chip intrinsic noise. By using double-gate MOSFETs for detectors in the near-IR band, noise performance in the readout circuitry is improved, thereby enhancing the overall performance of these detectors. A 1 dB reduction in low-frequency noise is achieved, which is verified through simulations. It is shown that by using short-channel devices that noise improvement is furthermore obtained due to reduction in threshold voltage variation. The double-gate concept is applied in simulation to the three-transistor pixel topology and can also be implemented in other detector topologies such as the four-transistor pixel topology, since readout noise is not limited to specific IR detector topologies. The overall performance of near-IR detectors and the fill factor are significantly improved. © (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only

Novel dual-threshold voltage FinFETs for circuit design and optimization

A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology

An Efficient Integrated Circuit Simulator And Time Domain Adjoint Sensitivity Analysis

In this paper, we revisit time-domain adjoint sensitivity with a circuit theoretic approach and an efficient solution is clearly stated in terms of device level. Key is the linearization of the energy storage elements (e.g., capacitance and inductance) and nonlinear memoryless elements (e.g., MOS, BJT DC characteristics) at each time step. Due to the finite precision of computation, numerical errors that accumulate across timesteps can arise in nonlinear elements

Novel IC designs with 32 nm Independent-Gate FinFET

Electrical EngineeringThe semiconductor industry is confronted with serious challenges as the push continues toward scaling transistors into the 22-nm technology node and beyond. The most important among these challenges is the diminishing gate control over the channel, which manifests itself in the form of the increased short-channel effects (SCE) and leakage currents. One approach to countering these effects is introducing new materials for improved performance, either into the gate stack, the channel, or the source/drain extension regions. However, even with the introduction of these new materials, leakage will continue to be a serious problem. Hence, alter device architecture are being explored which processes inherently better robustness to SCE. Among this alternatives, multiple-gate FETs, also known as FinFET or gate wrap-around FETs, are emerging as promising candidates. In a FinFET, the gate wraps around a thin slice of silicon, also known as a ???fin???, and current flows along the top and side surface of the fin. This wrap-around nature of the gate enhances the gate control over the channel, thus reducing the SCE and leakage currents. Furthermore, fabrication of FinFET is compatible with that of conventional CMOS, thus making possible very rapid deployment to manufacturing. From a circuit-design perspective, FinFET provides IC designer with more options to innovate. For instance, FinFET device can directly substitute the CMOS in the existing applications by using the shorted-gate FinFET in which two FinFET gates are tied together. Additionally, the low-power mode of FinFET device in which the back-gate bias is tied to a reverse-bias voltage is often employed in the low-power design in that it can reduce subthreshold leakage. Last but not least, the independent-gate FinFET emerges as an interesting device so that IC designers have a variety of choices to flexibly use the two gates of FinFET for difference tasks. In this thesis, independent-gate FinFET are our concern with two designs being included. The first work presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, a boosting structures is developed to improve the signal propagation on interconnect significantly. In the second work, a digital voltage sensor design is illustrated. Based on the operation of a p-type FinFET in low-power mode and independent-gate mode, a new technique for designing a controllable delay element (CDE) with high linearity is presented. Then, we develop a 9-bit digital voltage sensor with a voltage range of 0.7 ??? 1.1 V and 50 mV resolution. The proposed voltage sensor can operate with ultra-low power, a wide voltage range, and fairly high frequency.ope

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Silicon on Ferroelectric Insulator Field Effect Transistor (SOFFET): A Radical Alternative to Overcome the Thermionic Limit

Title from PDF of title page viewed January 3,2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 165-180)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 / at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high / current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 /. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 / and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.Introduction -- Subthreshold swing -- Multi-gate devices -- Tunneling field effect transistors -- I-mos & FET transistors -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for SOI-FINFET -- Multichannel tunneling carbon nanotube FET -- Partially depleted silicon-on-Ferroelectric insulator FET -- Fully depleted silicon-on-ferroelectric insulator FET -- Advantages, manufacturing process, and future work of the proposed devices -- Appendix A. Estimation of the body factor (n) [eta] of SOI FinFET -- Appendix B. Solution for the Poisson Equation of MT-CNTFE