Enabling Intra-Plane Parallel Block Erase to Alleviate the Impact of Garbage Collection

Garbage collection (GC) in NAND flash can significantly decrease I/O performance in SSDs by copying valid data to other locations, thus blocking incoming I/O requests. To help improve performance, NAND flash utilizes various advanced commands to increase internal parallelism. Currently, these commands only parallelize operations across channels, chips, dies, and planes, neglecting the block-level and below due structural bottlenecks along the data path and risk of disturbances that can compromise valid data by inducing errors. However, due to the triple-well structure of the NAND flash plane architecture and erasing procedure, it is possible to erase multiple blocks within a plane, in parallel, without being restricted by structural limitations or diminishing the integrity of the valid data. The number of page movements due to multiple block erases can be restrained so as to bound the overhead per GC. Moreover, more capacity can be reclaimed per GC which delays future GCs and effectively reduces their frequency. Such an Intra-Plane Parallel Block Erase (IPPBE) in turn diminishes the impact of GC on incoming requests, improving their response times. Experimental results show that IPPBE can reduce the time spent performing GC by up to 50.7% and 33.6% on average, read/write response time by up to 47.0%/45.4% and 16.5%/14.8% on average respectively, page movements by up to 52.2% and 26.6% on average, and blocks erased by up to 14.2% and 3.6% on average. An energy analysis conducted indicates that by reducing the number of page copies and the number of block erases, the energy cost of garbage collection can be reduced up to 44.1% and 19.3% on average

FRAM based low power systems for low duty cycle applications

Thesis (M.S.) University of Alaska Fairbanks, 2019Ferro-Electric Random Access Memory (FRAM) is a leap forward in non-volatile data storage technology for embedded systems. It allows for persistent storage without any power consumption, fulfilling the same role as flash memory. FRAM, however, provides several major advantages over flash memory, which can be leveraged to substantially reduce sleep current in a device. In applications where most of the time is spent sleeping these reductions can have a large impact on the average current. With careful design sleep currents as low as 72 nA have been demonstrated. A lower current consumption allows for more flexibility in deploying the device; smaller batteries or alternative power sources can be considered, and operating life can be extended. FRAM is not appropriate for every situation and there are some considerations to obtain the maximum benefit from its use. An MSP430FR2311 microcontroller is used to measure the performance of the FRAM and how to structure a program to achieve the lowest power consumption. Clock speed and instruction caching in particular have a large effect on the power consumption and tests are performed to quantify their effect. Two case studies are considered, a feedback control system and a data logger. Both cases involve large amounts of data writes and allow for the effects of the FRAM to be easily observed. Expected battery life is determined for each case when the sample rate is varied, suggesting that average operating current for the two solutions will nearly converge when the sampling period exceeds 1000 s. For sampling periods on the order of one second operating current can be reduced from 15.4 μA to 730 nA by utilizing FRAM in lieu of flash

Modeling and Implementation of HfO2-based Ferroelectric Tunnel Junctions

HfO2-based ferroelectric tunnel junctions (FTJs) represent a unique opportunity as both a next-generation digital non-volatile memory and as synapse devices in braininspired logic systems, owing to their higher reliability compared to filamentary resistive random-access memory (ReRAM) and higher speed and lower power consumption compared to competing devices, including phase-change memory (PCM) and state-of-the-art FTJ. Ferroelectrics are often easier to deposit and have simpler material structure than films for magnetic tunnel junctions (MTJs). Ferroelectric HfO2 also enables complementary metal-oxide-semiconductor (CMOS) compatibility, since lead zirconate titanate (PZT) and BaTiO3-based FTJs often are not. No other groups have yet demonstrated a HfO2-based FTJ (to best of the author’s knowledge) or applied it to a suitable system. For such devices to be useful, system designers require models based on both theoretical physical analysis and experimental results of fabricated devices in order to confidently design control systems. Both the CMOS circuitry and FTJs must then be designed in layout and fabricated on the same die. This work includes modeling of proposed device structures using a custom python script, which calculates theoretical potential barrier heights as a function of material properties and corresponding current densities (ranging from 8×10^3 to 3×10^(−2) A/cm2 with RHRS/RLRS ranging from 5×10^5 to 6, depending on ferroelectric thickness). These equations were then combined with polynomial fits of experimental timing data and implemented in a Verilog-A behavioral analog model in Cadence Virtuoso. The author proposes tristate CMOS control systems, and circuits, for implementation of FTJ devices as digital memory and presents simulated performance. Finally, a process flow for fabrication of FTJ devices with CMOS is presented. This work has therefore enabled the fabrication of FTJ devices at RIT and the continued investigation of them as applied to any appropriate systems

Power Efficient Data Compression Hardware for Wearable and Wireless Biomedical Sensing Devices

This thesis aims to verify a possible benefit lossless data compression and reduction techniques can bring to a wearable and wireless biomedical device, which is anticipated to be system power saving. A wireless transceiver is one of the main contributors to the system power of a wireless biomedical sensing device, and reducing the data transmitted by the transceiver with a minimum hardware cost can therefore help to save the power. This thesis is going to investigate the impact of the data compression and reduction on the system power of a wearable and wireless biomedical device and trying to find a proper compression technique that can achieve power saving of the device. The thesis first examines some widely used lossy and lossless data compression and reduction techniques for biomedical data, especially EEG data. Then it introduces a novel lossless biomedical data compression technique designed for this research called Log2 sub-band encoding. The thesis then moves on to the biomedical data compression evaluation of the Log2 sub-band encoding and an existing 2-stage technique consisting of the DPCM and the Huffman encoding. The next part of this thesis explores the signal classification potential of the Log2 sub-band encoding. It was found that some of the signal features extracted as a by-product during the Log2 sub-band encoding process could be used to detect certain signal events like epileptic seizures, with a proper method. The final section of the thesis focuses on the power analysis of the hardware implementation of two compression techniques referred to earlier, as well as the system power analysis. The results show that the Log2 sub-band is comparable and even superior to the 2-stage technique in terms of data compression and power performance. The system power requirement of an EEG signal recorder that has the Log2 sub-band implemented is significantly reduced