Advanced Coding And Modulation For Ultra-wideband And Impulsive Noises

The ever-growing demand for higher quality and faster multimedia content delivery over short distances in home environments drives the quest for higher data rates in wireless personal area networks (WPANs). One of the candidate IEEE 802.15.3a WPAN proposals support data rates up to 480 Mbps by using punctured convolutional codes with quadrature phase shift keying (QPSK) modulation for a multi-band orthogonal frequency-division multiplexing (MB-OFDM) system over ultra wideband (UWB) channels. In the first part of this dissertation, we combine more powerful near-Shannon-limit turbo codes with bandwidth efficient trellis coded modulation, i.e., turbo trellis coded modulation (TTCM), to further improve the data rates up to 1.2 Gbps. A modified iterative decoder for this TTCM coded MB-OFDM system is proposed and its bit error rate performance under various impulsive noises over both Gaussian and UWB channel is extensively investigated, especially in mismatched scenarios. A robust decoder which is immune to noise mismatch is provided based on comparison of impulsive noises in time domain and frequency domain. The accurate estimation of the dynamic noise model could be very difficult or impossible at the receiver, thus a significant performance degradation may occur due to noise mismatch. In the second part of this dissertation, we prove that the minimax decoder in \cite, which instead of minimizing the average bit error probability aims at minimizing the worst bit error probability, is optimal and robust to certain noise model with unknown prior probabilities in two and higher dimensions. Besides turbo codes, another kind of error correcting codes which approach the Shannon capacity is low-density parity-check (LDPC) codes. In the last part of this dissertation, we extend the density evolution method for sum-product decoding using mismatched noises. We will prove that as long as the true noise type and the estimated noise type used in the decoder are both binary-input memoryless output symmetric channels, the output from mismatched log-likelihood ratio (LLR) computation is also symmetric. We will show the Shannon capacity can be evaluated for mismatched LLR computation and it can be reduced if the mismatched LLR computation is not an one-to-one mapping function. We will derive the Shannon capacity, threshold and stable condition of LDPC codes for mismatched BIAWGN and BIL noise types. The results show that the noise variance estimation errors will not affect the Shannon capacity and stable condition, but the errors do reduce the threshold. The mismatch in noise type will only reduce Shannon capacity when LLR computation is based on BIL

Mixed-Signal Implementation of Low-Density Parity-Check Decoder

The receiver side of many communication systems incorporates an error-correction decoder to achieve good bit-error rate (BER) performance. While good BER is a metric of reliable communication, high throughput and energy-efficiency are also desired. Low-density parity-check (LDPC) decoders are able to perform well in term of these metrics. In this thesis, the Modified Differential Decoding Binary Message Passing (MDD-BMP) algorithm of LDPC codes has been chosen to implement in mixed-signal domain. The goal of this research is to achieve energy-efficiency in LDPC decoding while maintaining high-throughput in an implemented design of reasonable effective area. The re-design of some digital parts of the LDPC decoder in analog domain is expected to offer energy-efficiency and high throughput. However, these benefits come at a cost of analog impairments, such as, different random mismatch between similar inverters arising from process variation during fabrication. The comparative contribution of these impairments on the BER performance of the decoder has been investigated. During the design of the decoder, an on-chip calibration scheme has been arranged and global routing of the tuning signals has been maintained to address these random mismatches. Furthermore, modulation of the decoding speed by off-chip tuning has been made possible. For the purpose of high-speed testing of the decoding process, enough on-chip memory has been placed to store 10 codewords and feed them to the decoder through a binary-weighted capacitor-based digital to analog converter. Design and placement of analog MUXes enable us to debug sensitive analog nodes inside the decoder from off-chip. Finally, the full process of the physical design of the decoder in TSMC 65nm has been almost fully automated in Cadence SKILL code. Over 100 simulations including parasitic capacitance of long wires in physical design yield an average decoding speed of approximately 2.04 ns in moderate speed mode, therefore, providing a high throughput of 134 Gb/s. Taking into account the average current drawn by the circuits during both the pre-charge phase and the decoding phase, the calculated average energy per bit consumed by the decoder is 1.267 pJ/bit

Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

Iterative Detection and Phase-Noise Compensation for Coded Multichannel Optical Transmission

The problem of phase-noise compensation for correlated phase noise in coded multichannel optical transmission is investigated. To that end, a simple multichannel phase-noise model is considered and the maximum a posteriori detector for this model is approximated using two frameworks, namely factor graphs (FGs) combined with the sum–product algorithm (SPA), and a variational Bayesian (VB) inference method. The resulting pilot-aided algorithms perform iterative phase-noise compensation in cooperation with a decoder, using extended Kalman smoothing to estimate the a posteriori phase-noise distribution jointly for all channels. The system model and the proposed algorithms are verified using experimental data obtained from space-division multiplexed multicore-fiber transmission. Through Monte Carlo simulations, the algorithms are further evaluated in terms of phase-noise tolerance for coded transmission. It is observed that they significantly outperform the conventional approach to phase-noise compensation in the optical literature. Moreover, the FG/SPA framework performs similarly or better than the VB framework in terms of phase-noise tolerance of the resulting algorithms, for a slightly higher computational complexity

A Tutorial on Clique Problems in Communications and Signal Processing

Since its first use by Euler on the problem of the seven bridges of K\"onigsberg, graph theory has shown excellent abilities in solving and unveiling the properties of multiple discrete optimization problems. The study of the structure of some integer programs reveals equivalence with graph theory problems making a large body of the literature readily available for solving and characterizing the complexity of these problems. This tutorial presents a framework for utilizing a particular graph theory problem, known as the clique problem, for solving communications and signal processing problems. In particular, the paper aims to illustrate the structural properties of integer programs that can be formulated as clique problems through multiple examples in communications and signal processing. To that end, the first part of the tutorial provides various optimal and heuristic solutions for the maximum clique, maximum weight clique, and $k$-clique problems. The tutorial, further, illustrates the use of the clique formulation through numerous contemporary examples in communications and signal processing, mainly in maximum access for non-orthogonal multiple access networks, throughput maximization using index and instantly decodable network coding, collision-free radio frequency identification networks, and resource allocation in cloud-radio access networks. Finally, the tutorial sheds light on the recent advances of such applications, and provides technical insights on ways of dealing with mixed discrete-continuous optimization problems

Software-defined radio using LabVIEW and the PC sound card: A teaching platform for digital communications

Different modulation techniques and protocols require a standard communications laboratory for engineering courses to be equipped with a broad set of equipment, tools and accessories. However, the high costs involved in a hardware-based laboratory can become prohibitively expensive for many institutions. Software simulations alone can replicate most real-world applications with much lower costs. Nevertheless, they do not replace the real-world feeling provided by hardware-based systems, which can produce and receive physical signals to and from the exterior media. Advances in computer technology are allowing software-defined radio (SDR) concepts to be applied in many areas of communications. In this type of system, the baseband processing is performed completely in software while an analog RF front end hardware can be used for RF processing. The use of a software-defined radio platform in a digital communications laboratory can offer the benefits of software simulations coupled with the enthusiasm presented by hardware-based systems. A low-cost software-defined radio teaching platform implemented in LabVIEW using the personal computer sound card was developed for a digital communications laboratory along with a set of exercises to help students assimilate the concepts involved in communications theory and system implementation. This system allows for the generation, reception, processing, and analysis of signals in a 4 QAM (quadrature amplitude modulation) transceiver using the personal computer sound card to transmit and receive modulated signals. This teaching platform provides the means necessary to explore the theoretical concepts of digital communication systems in a laboratory environment. National Instruments\u27 LabVIEW graphical programming environment allows a more intuitive way of coding, which helps students to spend more time learning the relevant theory concepts and less time coding the applications. Being a flexible and modular system, modifications can be made for optimization and use with different and/or more complex techniques