Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The proposed model which is a mixed integer linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms of latency. Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks

Time-Sliced Quantum Circuit Partitioning for Modular Architectures

Current quantum computer designs will not scale. To scale beyond small prototypes, quantum architectures will likely adopt a modular approach with clusters of tightly connected quantum bits and sparser connections between clusters. We exploit this clustering and the statically-known control flow of quantum programs to create tractable partitioning heuristics which map quantum circuits to modular physical machines one time slice at a time. Specifically, we create optimized mappings for each time slice, accounting for the cost to move data from the previous time slice and using a tunable lookahead scheme to reduce the cost to move to future time slices. We compare our approach to a traditional statically-mapped, owner-computes model. Our results show strict improvement over the static mapping baseline. We reduce the non-local communication overhead by 89.8\% in the best case and by 60.9\% on average. Our techniques, unlike many exact solver methods, are computationally tractable.Comment: Appears in CF'20: ACM International Conference on Computing Frontier

Optimized Surface Code Communication in Superconducting Quantum Computers

Quantum computing (QC) is at the cusp of a revolution. Machines with 100 quantum bits (qubits) are anticipated to be operational by 2020 [googlemachine,gambetta2015building], and several-hundred-qubit machines are around the corner. Machines of this scale have the capacity to demonstrate quantum supremacy, the tipping point where QC is faster than the fastest classical alternative for a particular problem. Because error correction techniques will be central to QC and will be the most expensive component of quantum computation, choosing the lowest-overhead error correction scheme is critical to overall QC success. This paper evaluates two established quantum error correction codes---planar and double-defect surface codes---using a set of compilation, scheduling and network simulation tools. In considering scalable methods for optimizing both codes, we do so in the context of a full microarchitectural and compiler analysis. Contrary to previous predictions, we find that the simpler planar codes are sometimes more favorable for implementation on superconducting quantum computers, especially under conditions of high communication congestion.Comment: 14 pages, 9 figures, The 50th Annual IEEE/ACM International Symposium on Microarchitectur

Assessing the mapping of quantum algorithms on superconducting quantum processors

Quantum computing is a promising field regarding computation capabilities for several important tasks. One of the most promising solid-state quantum technology, which is being developed at Qutech (TU Delft), is superconducting qubits. In superconducting quantum processors, qubits are arranged along a 2D grid that only permits information transmission between adjacent qubits. In order to run a quantum algorithm on such a processor a mapping strategy of scheduling-placement-routing is needed.Quantum computers hold the promise for solving efficiently important problems in computational sciences that are intractable nowadays by exploiting quantum phenomena such are superposition and entanglement. Research in quantum computing is mainly driven by the development of quantum devices and quantum algorithms. Quantum algorithms can be described by quantum circuits, which are hardware agnostic -- e.g it is assumed that any arbitrary interaction between qubits is possible. However, real quantum processors have a series of constraints that must be complied to when running a quantum algorithm. Therefore, a mapping process that adapts the quantum circuit to chip's constraints is required. The mapping process will, in general, increase the number of gates and/or the circuit depth. As qubits and gates are error prone, it will result in an increment of the failure rate of computation while running the adapted quantum algorithm in a given quantum device. Most of the current mapping models optimize and are assessed based on two metrics: circuit depth (or latency) and number of (movement) operations added; they should be as minimal as possible. However, these metrics are not giving any information about how the mapping process is affecting the reliability of the algorithm. In other words, can still the algorithm produce `good' results after being mapped? The aim of this thesis is to propose some new mapping metrics that allow to study the impact of the mapping process on the algorithm's reliability. These are, quantum fidelity, probability of success of the algorithm and quantum volume. They could be used not only to assess the quality of the mapping procedure but also as parameters to be optimized by the mapping. To this purpose, different quantum algorithms have been mapped into the superconducting quantum processor, called Surface-17, developed at QuTech

Near-Optimal Fidelity in Quantum Circuits through Incorporating Efficient Real-time Error Based Heuristics in Compiler Mappings

To run a quantum program in the real device, the compiler maps the logical qubits to physical qubits. This is the most crucial step of compiling a quantum circuit. Because the fidelity of a quantum circuit depends heavily on this mapping process. However, this qubit mapping problem is NP-complete. Therefore, we should resort to heuristics to find high-fidelity mappings. In this paper, we focused on finding efficient heuristic techniques to incorporate real-time error feedback and device connectivity information in order to achieve high fidelity mapping of the quantum circuits. We performed extensive analysis and experimental study based on two baseline algorithms. We performed our experimentation on various combinations of different error rates and heuristic techniques. Consequently, we designed very elegant techniques to consider both all types of real-time error feedback and connectivity information. We showed that our best heuristic approach performs \textbf{1.62x} ( on average) better than one baseline and \textbf{1.934x} ( on average ) better than the other baseline on random benchmarks. Finally, we compared our best heuristic ( CAES ) with the state-of-the-art heuristic-based mapping algorithm on representative benchmarks. We found that CAES performed \textbf{1.7x} ( on average ) better than the state of the art in terms of success rate