Microscopic Analysis of Chips Security

Cílem této práce je vypracovat úvod do problematiky pouzdření, resp. odpouzdřování čipů. Dále zde můžete nalézt metodický postup k získání a rozpouzdření konkrétních čipů. Konečným výsledkem je získání snímků čipu pomocí mikroskopu a jejich následná analýza.The goal of this thesis is to work out an introduction to the chip packaging and decapsulation. Further can be found a description of a method leading to dacapsulate concrete chips. Final part is devoted to getting chip pictures using microscope and analysis of the pictures afterwards.

Pyramidal micromirrors for microsystems and atom chips

Concave pyramids are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micromirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into micro-optoelectromechanical systems and atom chips. We have shown that structures of this shape can be used to laser-cool and hold atoms in a magneto-optical trap

Profiling miniaturized separation media by micro infrared spectroscopy

Separation methods have been miniaturized in recent years. Capillary electrophoresis is now common and other types of analyses are being done on microfluidic chips with capillary channels in lieu of wider column diameters. The surfaces of the media used for separation are chemically modified. Using infrared spectroscopy by a microscope attachment, attempts were made to characterize the surfaces of both capillary channels and modified polymer for microfluidic chips. FTIR microscopy is not common in this type of analysis and is normally used to analyze particles, such as fibers, paint, and other polymer sources. Since modification of miniaturized chemical media is done on a microscopic scale, the FTIR microscope seemed promising for the detection of these changes. However, there was great difficulty in detecting the target material against the background material. Thus, micro-infrared spectroscopy is not an ideal method for characterizing modified separation media, despite its ability to sample small areas. Additionally, a novel medium for microfluidic chips, a material made of polymethylhydrosiloxane (PMHS), was described. PMHS has an advantage over other chip media in that the surface can be chemically modified, similar to capillary electrophoresis

Designing potentials by sculpturing wires

Magnetic trapping potentials for atoms on atom chips are determined by the current flow in the chip wires. By modifying the shape of the conductor we can realize specialized current flow patterns and therefore micro-design the trapping potentials. We have demonstrated this by nano-machining an atom chip using the focused ion beam technique. We built a trap, a barrier and using a BEC as a probe we showed that by polishing the conductor edge the potential roughness on the selected wire can be reduced. Furthermore we give different other designs and discuss the creation of a 1D magnetic lattice on an atom chip.Comment: 6 pages, 8 figure

Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)