The FTC's Challenge to Intel's Cross-Licensing Practices

After an investigation lasting several months, in June 1998 the Federal Trade Commission brought an antitrust lawsuit against Intel Corporation based on Intel's conduct towards Intergraph, and similar conduct towards Digital Equipment Corporation and Compaq, all in the context of disputes where Intel was accused of patent infringement. The FTC charged that Intel's practices were an abuse of Intel's monopoly position in microprocessors. Is Intel's conduct anti-competitive and thus illegal under the antitrust laws? That is the central question explored in this paper. An introductory section provides some background for the case by discussing the tension between intellectual property rights and antitrust law, a tension that is evident in the FTC's dispute with Intel, and by describing the role of patents in the semiconductor industry. Section 3 provides a succinct summary of the facts surrounding Intel's conduct in each of the three patent disputes identified by the FTC. Section 4 explains the FTC's theory of how Intel's conduct was anti-competitive. Section 5 presents Intel's response. Section 6 describes the settlement reached between the FTC and Intel. The final section discusses legal and economic developments since the case was settled and remarks on the lasting implications of the Intel case.

Micro-threading and FPGA implementation of a RISC microprocessor : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey University, Palmerston North, New Zealand

Appendix E removed due to copyright restrictions. Articles are available in the print copy held in the libraryThis thesis is the outcome of research in two areas of computer technology: microprocessor and multi-processor architectures (specifically from the perspective of how differently they tolerate highly-latent and non-deterministic events), and hardware design of complex digital systems containing both datapath and control (particularly microprocessors). This thesis starts by pointing out that in order to achieve high processing speeds, current popular superscalar microprocessors (e.g. Intel Pentiums, Digital Alpha, etc) rely heavily on the technique of speculating the outcome of instruction flow in order to predict the behaviour of non-deterministic computing operations (as in loading operands from high-latency memory into the processor). This is fine only if the speculation is correct. But, what if it isn't? If the speculation fails, this would mean that the processor has to abandon its current decision (which now proved to be the wrong one) for the instruction flow path taken and to start all over again with the other path (the actual correct one). This is a waste of valuable processing time and hardware resources and a reduction of performance when speculation fails. Therefore, these processors can achieve high performance only when the majority of speculations are successful (being able to predict the right path). In an attempt to overcome the above shortcomings, the first part of this thesis is an investigation of the novel vector micro-threading architecture as an alternative approach to the current superscalar-based speculative microprocessor designs. Micro-threading is based on the not-so-novel multithreading technique, which avoids speculation altogether and instead, starts running a different thread of instructions while waiting for the non-determinism to be resolved. This utilizes the chip resources more efficiently without waste of any processing power. The rest of this thesis focuses on the baseline RISC processor platform, the MIPS R2000, which is reviewed first then partially synthesized from the RTL (Register Transfer Level) description using VHDL and then simulated and tested. This is conducted in order for future research to build upon and add the micro-threading architectural add-ons and modifications. Keywords: Micro-threading, Latency Tolerance, FPGA Synthesis, RISC Architecture, MIPS R2000 processor, VHDL

The use of Petri nets for modeling pipelined processors

This paper discusses the use of Petri Nets for modeling and analyzing pipelined processors. Petri Nets are particularly well-suited to modeling the synchronization, buffering, resource contention and delicate timing so common in pipelined processors. Tools for simulating, animating and analyzing the behavior of the models are described. The usefulness of the tools and the analysis methods they support in evaluating the performance and analyzing the detailed timing of pipelined microprocessors is illustrated through an example

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data

Field-based branch prediction for packet processing engines

Network processors have exploited many aspects of architecture design, such as employing multi-core, multi-threading and hardware accelerator, to support both the ever-increasing line rates and the higher complexity of network applications. Micro-architectural techniques like superscalar, deep pipeline and speculative execution provide an excellent method of improving performance without limiting either the scalability or flexibility, provided that the branch penalty is well controlled. However, it is difficult for traditional branch predictor to keep increasing the accuracy by using larger tables, due to the fewer variations in branch patterns of packet processing. To improve the prediction efficiency, we propose a flow-based prediction mechanism which caches the branch histories of packets with similar header fields, since they normally undergo the same execution path. For packets that cannot find a matching entry in the history table, a fallback gshare predictor is used to provide branch direction. Simulation results show that the our scheme achieves an average hit rate in excess of 97.5% on a selected set of network applications and real-life packet traces, with a similar chip area to the existing branch prediction architectures used in modern microprocessors

Passive Heat Sink For Dynamic Thermal Management Of Hot Spots

A fully-passive, dynamically configurable directed cooling system for a microelectronic device is disclosed. In general, movable pins are suspended within a cooling plenum between an active layer and a second layer of the microelectronic device. In one embodiment, the second layer is another active layer of the microelectronic device. The movable pins are formed of a material that has a surface tension that decreases as temperature increases such that, in response to a temperature gradient on the surface of the active layer, the movable pins move by capillary flow in the directions of decreasing temperature. By moving in the direction of decreasing temperature, the movable pins move away from hot spots on the surface of the active layer, thereby opening a pathway for preferential flow of a coolant through the cooling plenum at a higher flow rate towards the hot spots.Georgia Tech Research Corporatio

Is Innovation King at the Antitrust Agencies? The Intellectual Property Guidelines Five Years Later

The Microsoft antitrust case focused public attention on the role of antitrust enforcement in preserving the forces of innovation in high-technology markets. Traditionally, regulators focused on whether companies artificially hiked prices or reduced output. Now, they're increasingly likely to look first at whether corporate behavior aids or impedes innovation. In this paper, we examine whether innovation has displaced short-term price effects as the focus of antitrust enforcement by the Department of Justice and the Federal Trade Commission and, to the extent that it has, whether enforcement actions are any different as a result. We also ask whether enforcement actions in the area of intellectual property and innovation have been consistent with the 1995 DOJ/FTC Antitrust Guidelines for the Licensing of Intellectual Property [IP Guidelines]. Finally, we consider whether recent enforcement actions identify key areas in which additional guidance from the Agencies would be desirable. We address these questions first in merger cases and then in non-merger cases.

On-chip micro-evaporation: Experimental evaluation of liquid pumping and vapor compression cooling systems

This paper was presented at the 3rd Micro and Nano Flows Conference (MNF2011), which was held at the Makedonia Palace Hotel, Thessaloniki in Greece. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, Aristotle University of Thessaloniki, University of Thessaly, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute.Thermal designers of data centers and server manufacturers are showing a great concern regarding the cooling of new generation data centers, which are more compact and dissipate more power than is currently possible to cool by conventional air conditioning systems. With very large data centers exceeding 100 000 servers, some consume more than 50 MW [1] of electrical energy to operate, energy which is directly converted to heat and then simply wasted as it is dissipated into the atmosphere. A potentially significantly better solution would be to make use of on-chip two-phase cooling [2], which, besides improving the cooling performance at the chip level, also adds the capability to reuse the waste heat in a convenient manner, since higher evaporating and condensing temperatures of the two-phase cooling system (from 60-95°C) are possible with such a new green cooling technology. In the present project, two such two-phase cooling cycles using micro-evaporation technology were experimentally evaluated with specific attention being paid to energy consumption, overall exergetic efficiency and controllability. The main difference between the two cooling cycles is the driver, where both a mini-compressor and a gear pump were considered. The former has the advantage due to its appeal of energy recovery since its exergy potential is higher and the waste heat is exported at a higher temperature for reuse.This study is supported by: the Swiss Commission for Technology and Innovation (CTI) contract number 6862.2; the LTCM laboratory; IBM Zürich Research Laboratory (Switzerland) and Embraco (Brazil)

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call