17,358 research outputs found

    On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

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    Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute- and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular, fault characterization and mitigation. By following a High-Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.Comment: 8 pages, 6 figure

    Asymmetric PCIe

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    Many devices such as accelerators, storage appliances, video transcoding accelerators, etc. have asymmetric bandwidth requirements. For example, the ingress bandwidth for a machine learning accelerator can be more than ten times the egress bandwidth. However, this asymmetry in bandwidth is not reflected in the interconnect. For example, PCI-express typically has as many lanes for host-to-device communications as it does for device-to-host communications. This disclosure presents techniques for asymmetric links between host and device. By reflecting the relative magnitudes of to-and-fro traffic more accurately, the asymmetric PCIe link achieves greater efficiency of communication

    Neural Networks for Modeling and Control of Particle Accelerators

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    We describe some of the challenges of particle accelerator control, highlight recent advances in neural network techniques, discuss some promising avenues for incorporating neural networks into particle accelerator control systems, and describe a neural network-based control system that is being developed for resonance control of an RF electron gun at the Fermilab Accelerator Science and Technology (FAST) facility, including initial experimental results from a benchmark controller.Comment: 21 p
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