Highly efficient frequency triplers in the millimeter wave region incorporating a back-to-back configuration of two varactor diodes

This paper reports on the recent development of monolithic frequency tripler array employing a back-to-back configuration of varactor diodes. Even harmonic idler circuits are unnecessary in this design. Furthermore, no external dc bias is required. The arrangement results in highly efficient, easily-fabricated and inexpensive frequency triplers

A robust high-efficiency cross-coupled charge pump circuit without blocking transistors

This document is the Accepted Manuscript version of the following article: Minglin Ma, Xinglong Cai, Yichuang Sun, and Nike George, ‘A robust high-efficiency cross-coupled charge pump circuit without blocking transistors’, Analog Integrated Circuits and Signal Processing, Vol. 95 (3): 395-401, June 2018. Under embargo until 16 March 2019. The final publication is available at Springer via: https://doi.org/10.1007/s10470-018-1149-xA fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.Peer reviewe

DESIGNING and ANALYSIS of GATES BASED on ADIABATIC LOGIC

Due to various advantages, CMOS are being widely used in designing of LSI(Large Scale Integration) & VLSI(Very Large Scale Integration).However there are some other sources present in CMOS which are responsible for the power dissemination that can be pigeonholed as follows: Dynamic Power Consumption, Short Circuit Currents, Leakage Current.To reduce this power consumption another CMOS logic family called the adiabatic switching logic based on adiabatic switching principle. The adiabatic logic structure significantly decreases the power scattering. The switching technique puts forward a methodology to reuse the energy put away in the load capacitors as opposed to the conventional method which used to release the energy of capacitors into the ground and squandering this energy.Presnt paper discusses the standards of adiabatic logic, its arrangement and classification of different adiabatic logic circuits. An endeavor has been made in this paper to change 2PASCL (Two Phase adiabatic Static CMOS Logic) adiabatic logic circuit by replacing the MOS diode with simple PN diode which decreases the impact of Capacitances at high  clock frequency

Current-voltage characteristics of TaSi2/Si and MOS devices using Labview

Analyses of current-voltage (LV) characteristics of Schottky Barrier Diodes (Tantalum Suicide) and Metal Oxide Semiconductor (MOS) Devices, using LabVIEWTM, has been presented here. LabVIEWTMTM, a graphical program development application, has been used to program a computer-driven Keithley Source Measure Unit (SMU) for device characterization. The SMU, which can be used as a Source Voltage - Measure Current as well as Source Current - Measure Voltage instrument, is used in the Source Voltage -Measure Current mode in this study. A General Purpose Interface Bus (GPIB) IEEE 488.2 has been used to interface the SMU with LabVIEWTMTM. LabVIEWTM has been successfully implemented to obtain the current-voltage characteristics of semiconductor devices, such as TaSi2 /Si and MOS structures. Based on this characterization, factors such as the barrier height for TaSi2 /Si and current conduction mechanisms in MOS device structures have been evaluated

A High Voltage Swing 1.9 GHz PA in Standard CMOS

A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nominal supply voltage is presented. To achieve this high-voltage tolerance the circuit implements switched-cascode transistors that yield reliable operation for voltages up to 7V at RF frequencies in a 2.5V CMOS process. Advantages of this include the possibility to use higherohmic load resistors. The impact of load resistances with higher ohmic values is two-fold. Firstly the demands on matching networks are loosened which translates into a higher efficiency for the matching network. Secondly the signal currents are lower which decreases the impact of any series resistance. A design of a 1.9 GHz power amplifier using the switched cascode approach was made. Simulations on the extracted layout of a single ended side showed 21 dBm of output power at a 25 ohm load with 21 % PAE. A layout improvement was estimated to result in 22 dBm at 30 % PAE