Novel Smart N95 Filtering Facepiece Respirator with Real-time Adaptive Fit Functionality and Wireless Humidity Monitoring for Enhanced Wearable Comfort

The widespread emergence of the COVID-19 pandemic has transformed our lifestyle, and facial respirators have become an essential part of daily life. Nevertheless, the current respirators possess several limitations such as poor respirator fit because they are incapable of covering diverse human facial sizes and shapes, potentially diminishing the effect of wearing respirators. In addition, the current facial respirators do not inform the user of the air quality within the smart facepiece respirator in case of continuous long-term use. Here, we demonstrate the novel smart N-95 filtering facepiece respirator that incorporates the humidity sensor and pressure sensory feedback-enabled self-fit adjusting functionality for the effective performance of the facial respirator to prevent the transmission of airborne pathogens. The laser-induced graphene (LIG) constitutes the humidity sensor, and the pressure sensor array based on the dielectric elastomeric sponge monitors the respirator contact on the face of the user, providing the sensory information for a closed-loop feedback mechanism. As a result of the self-fit adjusting mode along with elastomeric lining, the fit factor is increased by 3.20 and 5 times at average and maximum respectively. We expect that the experimental proof-of-concept of this work will offer viable solutions to the current commercial respirators to address the limitations.Comment: 20 pages, 5 figures, 1 table, submitted for possible publicatio

Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications

Approximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization

Low power digital baseband core for wireless Micro-Neural-Interface using CMOS sub/near-threshold circuit

This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of distributed sensors, is designed to control the operation of individual MNI and communicate and control MNI devices implanted across the brain using received downlink commands from external base station and store/dump targeted neural data uplink in an energy efficient manner. The application specific protocol defines three modes (Time Stamp Mode, Streaming Mode and Snippet Mode) to extract neural signals with on-chip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Ultra-low-power cell library containing 67 cells including physical cells and decoupling capacitor cells using the optimum fingers is designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32 size) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 μW, resulting in highest reported communication power efficiency of 290Kbps/μW to date

A 343nW biomedical signal acquisition system powered by energy efficient (62.8%) power aware RF energy harvesting circuit

This work proposes an energy efficient wearable CMOS biomedical signal acquisition and digitization scheme powered by RF energy harvesting circuit. The system consists of a ultra-low power analog front end (AFE) incorporating low noise instrumentation amplifier (IA)(CMRR=75dB), two programmable gain amplifiers (PGA), mixed signal automatic gain control (AGC) and a successive approximation register (SAR) analog to digital converter (ADC)(10-bit). The full system is powered by a power aware RF energy harvesting circuit for an input range of -26dBm to -8dBm. The AFE along with ADC consumes 343nA with 1V supply voltage in UMC 0.18μm CMOS technology

A 2 mu W Biomedical Frontend with Sigma Delta ADC for Self-powered U-Healthcare Devices in 0.18 mu m CMOS Technology

This paper presents an ultra-low power analog front end (AFE) with Sigma Delta modulator ADC meant for acquisition of biopotential signals. The system consists of a signal conditioning stage with programmable gain and bandwidth, a mixed signal automatic gain control (AGC), and a Sigma Delta ADC. The full system is designed in UMC 0.18 mu m CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47 mu W power consumption. The ADC provides 2 nd order noise shaping while using single integrator and an ENOB of similar to 12 bits with 1.4 similar to W power consumption. The system was successfully tested for a ECG signal from PTB database

A compact, low-power analog front-end with event-driven input biasing for high-density neural recording in 22-nm FDSOI

An ultra-small-area, low-power analog front-end (AFE) for high-density neural recording is presented in this paper. It features an 11-bit incremental delta-sigma analog-to-digital converter (σ ADC) enhanced with an offset-rejecting event-driven input biasing network. This network avoids saturation of the ADC input caused by leakage of the input-coupling capacitor implemented in an advanced technology node. Combining AC-coupling with direct data conversion, the proposed AFE can tolerate a rail-to-rail electrode offset and achieves a good trade-off between power, noise, bandwidth, input impedance, and area. Fabricated in a 22-nm fully-depleted silicon on insulator (FDSOI) process, the design occupies an active area of <0.001 mm2, the smallest obtained to this date for a neural AFE, and consumes <3 μW from a 0.8-V supply. It achieves an input-referred noise of 11.3 μVrms in the action potential band (300 Hz -10 kHz) and 10 μVrms in the local field potential band (1 Hz -300 Hz)

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax the power consumption of the ADCs and digital backend. Furthermore a fully integrated prototype of the analog front-end, containing a PLL, programmable clocking generator, analog pulse correlator, a linear-in-dB variable gain amplifier and a 4-bit ADC, is demonstrated. Several design decisions and techniques, like correlation with a windowed LO instead of with a matched template, exploiting the duty-cycled nature of the system, operation in the sub-1 GHz band as well as careful circuit design are employed to reach ultra-low power consumption. The analog front-end was manufactured in 130 nm CMOS and the active circuit area measures 1000 μ m× 1500 μm. A maximum channel conversion gain of 50 dB can be achieved. Two symbol rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps are supported. The AFE consumes 2.3 mA from a 1.2 V power supply when operating at 39.0625 Mpps. This corresponds to an energy consumption of 70 pJ/pulse. A wireless link over more than 10 m in an office-like environment has been demonstrated at 19.531 Mpps with a PER< 1E-3 under direct LOS conditions. © 2006 IEEE.status: publishe

System and Analog Front-End Design for Wireless Optogenetics and Marine Mammal Science

Thesis (Master's)--University of Washington, 2014The first part of this thesis will present a low-noise, low-power Analog Front-End (AFE) for acoustic and ocean pressure detection used in marine mammal science applications. First, the design of a test chip consisting of three AFE variations with a common two-stage amplifier will be analyzed. The primary goal for the first iteration chip was to explore the tradeoffs between noise and power as well as to perform basic interfacing with a hydrophone sensor; this in preparation for the second iteration system. The measured test results of this fabricated chip are discussed in detail. Second, a deployable system built upon the test chip and improved with several features such as power-gating, variable gain, and frequency scaling will be presented. This system includes digitization of sonar and pressure signals through an 8-bit successive approximation ADC. An SPI interface was added to the design in order to be compatible with a System-on-Chip developed by a collaborative team from the University of Virginia. In the second part of this work, a system for wireless optogenetics will be presented. First, an overview of the optogenetics science will be covered, as well as a brief description of the state-of-the-art stimulation systems used in this field. Next, a high-level overview of the proposed system will be presented followed by a detailed description of the main blocks. The last section will contain applicable metric measurements and the results obtained from an in-vivo experiment conducted using our system