The Virtual Bus: A Network Architecture Designed to Support Modular-Redundant Distributed Periodic Real-Time Control Systems

The Virtual Bus network architecture uses physical layer switching and a combination of space- and time-division multiplexing to link segments of a partial mesh network together on schedule to temporarily form contention-free multi-hop, multi-drop simplex signalling paths, or 'virtual buses'. Network resources are scheduled and routed by a dynamic distributed resource allocation mechanism with self-forming and self-healing characteristics. Multiple virtual buses can coexist simultaneously in a single network, as the resources allocated to each bus are orthogonal in either space or time. The Virtual Bus architecture achieves deterministic delivery times for time-sensitive traffic over multi-hop partial mesh networks by employing true line-speed switching; delays of around 15ns at each switching point are demonstrated experimentally, and further reductions in switching delays are shown to be achievable. Virtual buses are inherently multicast, with delivery skew across multiple destinations proportional to the difference in equivalent physical length to each destination. The Virtual Bus architecture is not a purely theoretical concept; a small research platform has been constructed for development, testing and demonstration purposes

An Overview of the AURORA Gigabit Testbed

AURORA is one of five U.S. testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. AURORA is also an experiment in collaboration, where government support (through the Corporation for National Research Initiatives, which is in turn funded by DARPA and the NSF) has spurred interaction among centers of excellence in industry, academia, and government. The emphasis of the AURORA testbed, distinct from the other four testbeds, is research into the supporting technologies for gigabit networking. Our targets include new software architectures, network abstractions, hardware technologies, and applications. This paper provides an overview of the goals and methodologies employed in AURORA, and reports preliminary results from our first year of research

The AURORA Gigabit Testbed

AURORA is one of five U.S. networking testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. The emphasis of the AURORA testbed, distinct from the other four testbeds, BLANCA, CASA, NECTAR, and VISTANET, is research into the supporting technologies for gigabit networking. Like the other testbeds, AURORA itself is an experiment in collaboration, where government initiative (in the form of the Corporation for National Research Initiatives, which is funded by DARPA and the National Science Foundation) has spurred interaction among pre-existing centers of excellence in industry, academia, and government. AURORA has been charged with research into networking technologies that will underpin future high-speed networks. This paper provides an overview of the goals and methodologies employed in AURORA, and points to some preliminary results from our first year of research, ranging from analytic results to experimental prototype hardware. This paper enunciates our targets, which include new software architectures, network abstractions, and hardware technologies, as well as applications for our work

Cycle-accurate multicore performance models on FPGAs

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 159-165).The goal of this project is to improve computer architecture by accelerating cycle-accurate performance modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with realistic On-Chip Networks.by Michael Pellauer.Ph.D

Design, analysis and implementation of integrated services networks.

by Wong, Chan-foon.Thesis (M.Phil.)--Chinese University of Hong Kong, 1993.Includes bibliographical references (leaves 59-67 (1st gp.)).Chapter Chapter I --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Traffic Characteristics --- p.2Chapter 1.3 --- Related Works --- p.5Chapter Chapter II --- Integrated Services Protocol (ISP) --- p.7Chapter 2.1 --- Ethernet --- p.7Chapter 2.2 --- ISP Description --- p.9Chapter 2.2.1 --- Voice Communications Characteristics --- p.9Chapter 2.2.2 --- Voice Packet Format --- p.12Chapter 2.2.3 --- Call Management --- p.13Chapter 2.4.4 --- Voice Packet Transmission Protocol --- p.14Chapter 2.4.5 --- Error Handling --- p.16Chapter Chapter III --- Protocol Studies --- p.17Chapter 3.1 --- Simulation Model And Parameters --- p.17Chapter 3.2 --- Voice Loss --- p.18Chapter 3.3 --- Data Delay --- p.20Chapter 3.4 --- Maximum Number Of Active Voice Stations --- p.22Chapter 3.5 --- Summary --- p.23Chapter Chapter IV --- Implementation --- p.24Chapter 4.1 --- System Platform --- p.24Chapter 4.2 --- Integrated Services Adapter (ISA) --- p.25Chapter 4.2.1 --- Hardware Design --- p.26Chapter 4.3 --- Voice on Ethernet Adapter (VEA) --- p.29Chapter 4.3.1 --- Hardware Design --- p.29Chapter 4.3.2 --- Software Design --- p.31Chapter 4.3.2.1 --- Programming The VEA --- p.32Chapter 4.3.2.2 --- Software Development Under DOS --- p.35Chapter 4.3.2.3 --- Software Development Under Linux --- p.37Chapter 4.4 --- Summary --- p.41Chapter Chapter V --- Implementation Results --- p.42Chapter 5.1 --- Frequency Response --- p.43Chapter 5.2 --- Distortion --- p.44Chapter 5.3 --- Amplification and Linearity --- p.45Chapter 5.4 --- Voice Quality With Different Voice Packet Sizes --- p.46Chapter 5.5 --- Voice Loss Under Various Data Loadings --- p.47Chapter Chapter VI --- Implementation Experiences --- p.49Chapter 6.1 --- CPU Bottle-neck --- p.49Chapter 6.2 --- Data Bus Bottle-neck --- p.50Chapter 6.3 --- Operating System --- p.50Chapter Chapter VII --- Future Works --- p.52Chapter 7.1 --- Enhancement of ISA --- p.52Chapter 7.2 --- Extensions To Other Networks --- p.53Chapter 7.3 --- A New Architecture For Future Multimedia Workstation --- p.54Chapter Chapter VIII --- Conclusions --- p.57Bibliography --- p.59Appendices --- p.A.lAppendix A: Detailed Circuit Designs --- p.A.2Appendix B: Detailed Software Designs --- p.A.5Appendix C: Schematic Diagrams --- p.A.15Appendix D: Program Listings --- p.A.2

Development and characterisation of the radiation tolerant HELIX 128-2 readout chip for the HERA-B microstrip detectors

In der vorliegenden Doktorarbeit wurden große Teile der Schaltung des Verstärker- und Auslesechips HELIX128-2 entwickelt. Dazu gehörten unter anderem der 'Bias Generator', eine Schaltung zur Einstellung der Ruheströme und Kontrollspannungen der Verstärkerstufen mit Digital-zu-Analog Wandlern, sowie eine serielle Schnittstelle zum Programmieren der Betriebsparameter des Chips. Des weiteren wurde eine vollständige Charakterisierung des Chips, einschließlich der Bestrahlung mit einer 137Cs-Quelle durchgeführt. Die bei den dazu notwendigen Tests und Messungen gefundenen Unzulänglichkeiten führten zu einer Weiterentwicklung des Chips in verschiedenen Revisionsstufen: 2.2, 2.3, 3.0, 3.1 und 3.1a. Die dabei eingeflossenen Modifikationen betrafen mit Ausnahme von Eingangsstufe und Multiplexer alle Schaltungsteile. Insbesondere an der Pipeline Schreib-/Lesesteuerung wurden im Rahmen dieser Arbeit Verbesserungen vorgenommen. HELIX128-2 ist eine rauscharme (ENC = 462e+35.4e/pF für einen neuen Chip, ENC = 571e+52.0e/pF nach 3.9kGy) VLSI-Schaltung zur Auslese von 128 Kanälen eines Silizium-Streifenzählers oder einer MSGC. Die Architektur implementiert neben einem analogen Auslesepfad, der dem Konzept des CERN RD20/FElix Chip folgt (Ladungsverstärker, Pulsformer, analoger Zwischenspeicher und serielle Auslese der Kanäle getriggerter Daten) auch über einen unverzögerten binären Datenpfad. Er ist für Triggeranwendungen gedacht und über der Eingangsstufe folgende Komparatoren realisiert, deren Signale in Gruppen von vier Kanälen zusammengefaßt werden. Die vorliegende Arbeit gliedert sich daher in zwei Teile: Der erste Teil ist die Beschreibung des HELIX128-2 mit besonderem Schwerpunkt auf der Schaltungsimplementation. Der zweite Teil gibt die Ergebnisse der Charakterisierung des Chips wieder und beinhaltet die Chipeigenschaften unter Bestrahlung bis 3.9kGy