Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA

Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper,we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliabilityComment: 6 pages, 8 figures, conferenc

Fault-Tolerant Nanosatellite Computing on a Budget

Computer Systems, Imagery and Medi

Magnetic Graphene Memory Circuit Characterization And Verilog-A Modeling

Memory design plays an important role in modern computer technology in regard to overall performance and reliability. Prior memory technologies, including magneticcore memory, hard disk drives, DRAM, SRAM have limitations in regard to bit density, IC integration, power efficiency, and physical size, respectively. To address these limitations we propose to develop a magnetic graphene random access memory (MGRAM) utilizing graphene Hall effect, which takes advantage of the inherent reliability of magnetic memory and superior electrical properties of graphene (high carrier mobility, zero-band gap, high Hall sensitivity). As the graphene magnetic memory device will be integrated with a CMOS ASIC design an analog circuit model for the MGRAM cell is necessary and important. In this study the electrical circuit model is developed utilizing the analog circuit modeling language Verilog-A. The electrical circuit model characterizes the graphene electrical properties and the ferromagnetic core magnetic properties that retains the bit-state value. MGRAM device simulations studying varying coil width, height, radius, contact pad configuration, graphene shape, is performed with the MagOasis Magsimus tool to evaluate the device performance. Model results show a maximum Hall effect voltage of 100mV for a bias current of 50uA with a 1 Tesla magnetic field, and a writing speed of 6-9ns for setting the magnetic state. These results will be validated against the circuit hardware measurement and will be used for model refinement

Cross-layer Soft Error Analysis and Mitigation at Nanoscale Technologies

This thesis addresses the challenge of soft error modeling and mitigation in nansoscale technology nodes and pushes the state-of-the-art forward by proposing novel modeling, analyze and mitigation techniques. The proposed soft error sensitivity analysis platform accurately models both error generation and propagation starting from a technology dependent device level simulations all the way to workload dependent application level analysis

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi