9 research outputs found
Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)
Finite field multiplier is mainly used in elliptic curve cryptography,
error-correcting codes and signal processing. Finite field multiplier is
regarded as the bottleneck arithmetic unit for such applications and it is the
most complicated operation over finite field GF(2m) which requires a huge
amount of logic resources. In this paper, a new modified serial-in parallel-out
multiplication algorithm with interleaved modular reduction is suggested. The
proposed method offers efficient area architecture as compared to proposed
algorithms in the literature. The reduced finite field multiplier complexity is
achieved by means of utilizing logic NAND gate in a particular architecture.
The efficiency of the proposed architecture is evaluated based on criteria such
as time (latency, critical path) and space (gate-latch number) complexity. A
detailed comparative analysis indicates that, the proposed finite field
multiplier based on logic NAND gate outperforms previously known resultsComment: 19 pages, 4 figure
Recommended from our members
Fast Galois field arithmetic for elliptic curve cryptography and error control codes
Today's computer and network communication systems rely on authenticated and
secure transmission of information, which requires computationally efficient and
low bandwidth cryptographic algorithms. Among these cryptographic algorithms
are the elliptic curve cryptosystems which use the arithmetic of finite fields. Furthermore,
the fields of characteristic two are preferred since they provide carry-free
arithmetic and at the same time a simple way to represent field elements on current
processor architectures.
Arithmetic in finite field is analogous to the arithmetic of integers. When
performing the multiplication operation, the finite field arithmetic uses reduction
modulo the generating polynomial. The generating polynomial is an irreducible
polynomial over GF(2), and the degree of this polynomial determines the size of
the field, thus the bit-lengths of the operands.
The fundamental arithmetic operations in finite fields are addition, multiplication,
and inversion operations. The sum of two field elements is computed very
easily. However, multiplication operation requires considerably more effort compared
to addition. On the other hand, the inversion of a field element requires much
more computational effort in terms of time and space. Therefore, we are mainly interested in obtaining implementations of field multiplication and inversion.
In this dissertation, we present several new bit-parallel hardware architectures with low space and time complexity. Furthermore, an analysis and refinement of the complexity of an existing hardware algorithm and a software method highly efficient and suitable for implementation on many 32-bit processor architectures are also described
Implementaciones hardware de circuitos aritméticos sobre cuerpos finitos (Hardwareimolementations of arithmetic circuits over finite field)
La aritmética sobre cuerpos finitos ha recibido mucho interés debido a su importancia en criptografía, control de errores de codificación y procesado de señales digitales. Una gran parte del tiempo de las rutinas criptográficas se dedica al cálculo de operaciones aritméticas sobre cuerpos finitos. Los sistemas que usan esta aritmética deben ser
rápidos debido a los rendimientos requeridos en los sistemas de comunicación actuales. La suma en GF(2^m) es una operación XOR binaria independiente, puede ser realizada de forma rápida y sin retardo. Sin embargo otras operaciones son mucho más complejas y con mayor retardo. La eficiencia de las implementaciones hardware se mide en términos del número de puertas (XOR y AND) y del retardo total debido a esas puertas del circuito. El objetivo de este documento es hacer un estudio comparativo de diferentes circuitos aritméticos sobre GF(2^m), se utilizarán los cuerpos recomendados por el NIST y el SECG. Por su importancia, se han estudiado diferentes implementaciones para los algoritmos de multiplicación, tanto multiplicación serie como paralela junto con multiplicación dígito serie. Para el estudio de toras operaciones aritméticas, también se estudian algoritmos para obtener el cuadrado y el inverso de elementos pertencientes a GF(2^m). Para realizar este trabajo se implentarán los algoritmos mencionados en VHDL para FPGAs estudiando el consumo de área y tiempo de las operaciones comparando los resultados entre sí y con los obtenidos por otros autores. [ABSTRACT]Finite field arithmetic has received much attention due to its importance in cryptography, error control coding and digital signal processing. A large portion of time from
the routines of the cryptographies algorithms is used in the calculation of arithmetic operations on finite fields. Systems using this arithmetic must be faster because of
performance required in current communication systems. Addition in GF(2^m) is bit independent XOR operation, it can be implemented in fast and inexpensive ways. Nevertheless other operations are much more complex and expensive. The efficiency of the hardware implementations is measured in terms of the numbers of gates (XOR and AND) and of the total gate delay of the circuit. The aim of this document is to make a comparative study of different arithmetic circuits over GF(2^m), NIST and SECG recommended fields will be used. Due to multiplication is one of the most complex and important operation in finite field arithmetic, different implementations will be treated, parallel and serial along with digit-serial algorithms. To perform other operations, also inversion and square algorithms over GF(2^m)
have been discussed. VHDL implementations of these algorithms for FPGAs have been realized to study time and area consumption and to compare the result each other and with other authors'results
Normal Basis Multiplication Algorithms for GF(2n) (Full Version)
In this paper, we propose a new normal basis multiplication algorithm for GF(2n). This algorithm can be used to design not only fast software algorithms but also low complexity bit-parallel multipliers in some GF(2n)s. Especially, for some values of n that no Gaussian normal basis exists in GF(2n), i.e., 8|n, this algorithm provides an alternative way to construct low complexity normal basis multipliers. Two improvements on a recently proposed software normal basis multiplication algorithm are also presented. Time and memory complexities of these normal basis multiplication algorithms are compared with respect to software performance. It is shown that they have some specific behavior in different applications. For example, GF(2571) is one of the five binary fields recommended by NIST for ECDSA (Elliptic Curve Digital Signature Algorithm) applications. In this field, our experiments show that the new algorithm is even faster than the polynomial basis Montgomery multiplication algorithm: 525 us v. 819 us
Low Complexity Finite Field Multiplier for a New Class of Fields
Finite fields is considered as backbone of many branches in number theory, coding theory, cryptography, combinatorial designs, sequences, error-control codes, and algebraic geometry. Recently, there has been considerable attention over finite field arithmetic operations, specifically on more efficient algorithms in multiplications. Multiplication is extensively utilized in almost all branches of finite fields mentioned above. Utilizing finite field provides an advantage in designing hardware implementation since the ground field operations could be readily converted to VLSI design architecture. Moreover, due to importance and extensive usage of finite field arithmetic in cryptography, there is an obvious need for better and more efficient approach in implementation of software and/or hardware using different architectures in finite fields. This project is intended to utilize a newly found class of finite fields in conjunction with the Mastrovito algorithm to compute the polynomial multiplication more efficiently
A new approach in building parallel finite field multipliers
A new method for building bit-parallel polynomial basis finite field multipliers is proposed in this thesis. Among the different approaches to build such multipliers, Mastrovito multipliers based on a trinomial, an all-one-polynomial, or an equally-spacedpolynomial have the lowest complexities. The next best in this category is a conventional multiplier based on a pentanomial. Any newly presented method should have complexity results which are at least better than those of a pentanomial based multiplier. By applying our method to certain classes of finite fields we have gained a space complexity as n2 + H - 4 and a time complexity as TA + ([ log2(n-l) ]+3)rx which are better than the lowest space and time complexities of a pentanomial based multiplier found in literature. Therefore this multiplier can serve as an alternative in those finite fields in which no trinomial, all-one-polynomial or equally-spaced-polynomial exists
Efficient Implementation of Elliptic Curve Cryptography on FPGAs
This work presents the design strategies of an FPGA-based elliptic curve co-processor. Elliptic curve cryptography is an important topic in cryptography due to its relatively short key length and higher efficiency as compared to other well-known public key crypto-systems like RSA. The most important contributions of this work are: - Analyzing how different representations of finite fields and points on elliptic curves effect the performance of an elliptic curve co-processor and implementing a high performance co-processor. - Proposing a novel dynamic programming approach to find the optimum combination of different recursive polynomial multiplication methods. Here optimum means the method which has the smallest number of bit operations. - Designing a new normal-basis multiplier which is based on polynomial multipliers. The most important part of this multiplier is a circuit of size for changing the representation between polynomial and normal basis
Role of Cryptographic Welch-Gong (WG-5) Stream Cipher in RFID Security
The purpose of this thesis is to design a secure and optimized cryptographic stream cipher for passive type Radio Frequency Identification (RFID) tags.
RFID technology is a wireless automatic tracking and identification device. It has become an integral part of our daily life and it is used in many applications such as electronic passports, contactless payment systems, supply chain management and so on. But the information carried on RFID tags are vulnerable to unauthorized access (or various threats) which raises the security
and privacy concern over RFID devices. One of the possible solutions to protect the confidentiality, integrity and to provide authentication is, to use a cryptographic stream cipher which encrypts the original information with a pseudo-random bit sequence. Besides that RFID tags
require a resource constrained environment such as efficient area, power and high performance cryptographic systems with large security margins. Therefore, the architecture of stream cipher
provides the best trade-off between the cryptographic security and the hardware efficiency.
In this thesis, we first described the RFID technology and explain the design requirements for passive type RFID tags. The hardware design for passive tags is more challenging due to its stringent requirements like power consumption and the silicon area. We presented different design measures and some of the optimization techniques required to achieve low-resource
cryptographic hardware implementation for passive tags.
Secondly, we propose and implement a lightweight WG-5 stream cipher, which has good proven cryptographic mathematical properties. Based on these properties we measured the security analysis of WG-5 and showed that the WG-5 is immune to different types of attacks such as algebraic attack, correlation attack, cube attack, differential attack, Discrete Fourier Transform attack (DFT), Time-Memory-Data trade-off attack. The implementation of WG-5 was carried out using 65 nm and 130 nm CMOS technologies. We achieved promising results of WG-5 implementation in terms of area, power, speed and optimality. Our results outperforms most of the other stream ciphers which are selected in eSTREAM project.
Finally, we proposed RFID mutual authentication protocol based on WG-5. The security and privacy analysis of the proposed protocol showed that it is resistant to various RFID attacks such
as replay attacks, Denial-of-service (DoS) attack, ensures forward privacy and impersonation attack
Automated Design Space Exploration and Datapath Synthesis for Finite Field Arithmetic with Applications to Lightweight Cryptography
Today, emerging technologies are reaching astronomical proportions. For example, the Internet
of Things has numerous applications and consists of countless different devices using different
technologies with different capabilities. But the one invariant is their connectivity. Consequently,
secure communications, and cryptographic hardware as a means of providing them, are faced
with new challenges. Cryptographic algorithms intended for hardware implementations must be
designed with a good trade-off between implementation efficiency and sufficient cryptographic
strength. Finite fields are widely used in cryptography. Examples of algorithm design choices
related to finite field arithmetic are the field size, which arithmetic operations to use, how to
represent the field elements, etc. As there are many parameters to be considered and analyzed, an
automation framework is needed.
This thesis proposes a framework for automated design, implementation and verification of finite
field arithmetic hardware. The underlying motif throughout this work is “math meets hardware”.
The automation framework is designed to bring the awareness of underlying mathematical
structures to the hardware design flow. It is implemented in GAP, an open source computer algebra
system that can work with finite fields and has symbolic computation capabilities. The framework
is roughly divided into two phases, the architectural decisions and the automated design genera-
tion. The architectural decisions phase supports parameter search and produces a list of candidates.
The automated design generation phase is invoked for each candidate, and the generated VHDL
files are passed on to conventional synthesis tools. The candidates and their implementation results
form the design space, and the framework allows rapid design space exploration in a systematic
way. In this thesis, design space exploration is focused on finite field arithmetic.
Three distinctive features of the proposed framework are the structure of finite fields, tower field
support, and on the fly submodule generation. Each finite field used in the design is represented as
both a field and its corresponding vector space. It is easy for a designer to switch between fields
and vector spaces, but strict distinction of the two is necessary for hierarchical designs. When an
expression is defined over an extension field, the top-level module contains element signals and
submodules for arithmetic operations on those signals. The submodules are generated with
corresponding vector signals and the arithmetic operations are now performed on the coordinates.
For tower fields, the submodules are generated for the subfield operations, and the design is generated
in a top-down fashion. The binding of expressions to the appropriate finite fields or vector spaces
and a set of customized methods allow the on the fly generation of expressions for implementation
of arithmetic operations, and hence submodule generation.
In the light of NIST Lightweight Cryptography Project (LWC), this work focuses mainly on small
finite fields. The thesis illustrates the impact of hardware implementation results during the design
process of WAGE, a Round 2 candidate in the NIST LWC standardization competition. WAGE
is a hardware oriented authenticated encryption scheme. The parameter selection for WAGE was
aimed at balancing the security and hardware implementation area, using hardware implementation
results for many design decisions, for example field size, representation of field elements, etc.
In the proposed framework, the components of WAGE are used as an example to illustrate different
automation flows and demonstrate the design space exploration on a real-world algorithm