Run-Time Adaptable On-Chip Predictive Thermal Triggers

With ever-increasing power densities, Dynamic Thermal Management (DTM) techniques have become mainstream in today’s systems. An important component of such techniques is the thermal trigger. It has been shown that predictive thermal triggers can outperform reactive ones. In this paper, we present a novel trade-off space of predictive thermal triggers, and identify run-time adaptability as a crucial parameter of interest. We identify the Neural Network (NN) simulator presented in [14] to have some key advantages over other predictive thermal triggers. We extend it to work for an arbitrary sensor layout configuration and to be run-time adaptable. We present experimental results on Niagara UltraSPARC T1 chip with real-life benchmark applications. Our results validate our proposed extension of the NN simulator. Our results also quantitatively establish the effectiveness of the proposed simulator for reducing, the otherwise unacceptably high errors, that can arise due to expected leakage current variation and design-time thermal modelling errors

Low Power Sequential Circuit Design by Using Priority Encoding and Clock Gating

This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Practical design examples are studied and simulated by PSPICE. Experimental results demonstrate that the priority encoding technique can result in sizable power saving