MOVING OBJECT DETECTION WITH MEMRISTIVE CROSSBAR ARRAYS

This thesis is dedicated to the hardware implementation of a novel moving object detection algorithm. Proposed circuit includes several stages, each of which implements a particular step of the algorithm. Four higher bit planes are extracted from a grayscale image and stored in memristive crossbar arrays, and the respective bit planes are compared via memristive threshold logic gates in XOR configuration. In the next stage, compared bit planes are combined by weighted summation, with a highest weight assigned to MSB plane and smaller weights for less significant bit planes. After summation stage, obtained grayscale image is thresholded to obtain binary image. The last stage is implemented via memristive content-addressable memory array, which serves two purposes. It is used as a long-term memory in comparison to crossbar arrays, which serve as a short-term memory of proposed circuit. Content-addressable memory is updated based on the row-by-row difference between first and second pair of frames processed by previous stages. It also allows for analysis of object movement direction and velocity by observing the row capacitors’ discharge. Simulations show that accuracy of proposed circuit operation is increased with the larger array size. Delay analysis of the circuit is carried out, power and area calculations show that proposed circuit is a viable candidate as a co-processing operator for existing image sensors

DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible